Searched refs:XUSB_PADCTL_UPHY_PLL_P0_CTL1_PWR_OVRD (Results 1 – 1 of 1) sorted by relevance
178 #define XUSB_PADCTL_UPHY_PLL_P0_CTL1_PWR_OVRD (1 << 4) macro234 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL1_PWR_OVRD; in pcie_phy_enable()377 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_PWR_OVRD; in pcie_phy_enable()