Searched refs:XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV_MASK (Results 1 – 1 of 1) sorted by relevance
174 #define XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV_MASK (0xff << 20) macro254 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_NDIV_MASK; in pcie_phy_enable()