Searched refs:XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_MDIV_MASK (Results 1 – 1 of 1) sorted by relevance
176 #define XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_MDIV_MASK (0x3 << 16) macro253 value &= ~XUSB_PADCTL_UPHY_PLL_P0_CTL1_FREQ_MDIV_MASK; in pcie_phy_enable()