Searched refs:XUSB_PADCTL_UPHY_PLL_P0_CTL1_ENABLE (Results 1 – 1 of 1) sorted by relevance
179 #define XUSB_PADCTL_UPHY_PLL_P0_CTL1_ENABLE (1 << 3) macro311 value |= XUSB_PADCTL_UPHY_PLL_P0_CTL1_ENABLE; in pcie_phy_enable()