Searched refs:XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_MDIV_MASK (Results 1 – 1 of 1) sorted by relevance
176 #define XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_MDIV_MASK 0x3 macro523 value &= ~((XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_MDIV_MASK << in tegra210_pex_uphy_enable()776 value &= ~((XUSB_PADCTL_UPHY_PLL_CTL1_FREQ_MDIV_MASK << in tegra210_sata_uphy_enable()