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Searched refs:XUSB (Results 1 – 15 of 15) sorted by relevance

/openbmc/linux/Documentation/devicetree/bindings/usb/
H A Dnvidia,tegra124-xusb.yaml14 exposed by the Tegra XUSB pad controller.
31 - description: base and length of the XUSB FPCI registers
47 - description: XUSB host clock
48 - description: XUSB host source clock
49 - description: XUSB Falcon source clock
50 - description: XUSB SuperSpeed clock
51 - description: XUSB SuperSpeed clock divider
52 - description: XUSB SuperSpeed source clock
53 - description: XUSB HighSpeed clock source
54 - description: XUSB FullSpeed clock source
[all …]
H A Dnvidia,tegra210-xusb.yaml14 exposed by the Tegra XUSB pad controller.
23 - description: base and length of the XUSB FPCI registers
39 - description: XUSB host clock
40 - description: XUSB host source clock
41 - description: XUSB Falcon source clock
42 - description: XUSB SuperSpeed clock
43 - description: XUSB SuperSpeed clock divider
44 - description: XUSB SuperSpeed source clock
45 - description: XUSB HighSpeed clock source
46 - description: XUSB FullSpeed clock source
[all …]
H A Dnvidia,tegra234-xusb.yaml15 the Tegra XUSB pad controller. The xHCI controller controls up to eight
25 - description: XUSB FPCI registers
26 - description: XUSB bar2 registers
41 - description: XUSB host clock
42 - description: XUSB Falcon source clock
43 - description: XUSB SuperSpeed clock
44 - description: XUSB SuperSpeed source clock
45 - description: XUSB HighSpeed clock source
46 - description: XUSB FullSpeed clock source
78 description: phandle to the XUSB pad controller that is used to configure
H A Dnvidia,tegra-xudc.yaml7 title: NVIDIA Tegra XUSB device mode controller (XUDC)
30 - description: XUSB device controller registers
31 - description: XUSB device PCI Config registers
32 - description: XUSB device registers.
43 description: Must contain the XUSB device interrupt.
48 - description: Clock to enable core XUSB dev clock.
49 - description: Clock to enable XUSB super speed clock.
50 - description: Clock to enable XUSB super speed dev clock.
51 - description: Clock to enable XUSB high speed dev clock.
52 - description: Clock to enable XUSB full speed dev clock.
[all …]
H A Dnvidia,tegra186-xusb.yaml14 exposed by the Tegra XUSB pad controller.
23 - description: base and length of the XUSB FPCI registers
37 - description: XUSB host clock
38 - description: XUSB Falcon source clock
39 - description: XUSB SuperSpeed clock
40 - description: XUSB SuperSpeed source clock
41 - description: XUSB HighSpeed clock source
42 - description: XUSB FullSpeed clock source
74 description: phandle to the XUSB pad controller that is used to configure
H A Dnvidia,tegra194-xusb.yaml14 exposed by the Tegra XUSB pad controller.
23 - description: base and length of the XUSB FPCI registers
37 - description: XUSB host clock
38 - description: XUSB Falcon source clock
39 - description: XUSB SuperSpeed clock
40 - description: XUSB SuperSpeed source clock
41 - description: XUSB HighSpeed clock source
42 - description: XUSB FullSpeed clock source
74 description: phandle to the XUSB pad controller that is used to configure
/openbmc/linux/Documentation/devicetree/bindings/pinctrl/
H A Dnvidia,tegra124-xusb-padctl.txt1 Device tree binding for NVIDIA Tegra XUSB pad controller
4 NOTE: It turns out that this binding isn't an accurate description of the XUSB
10 The Tegra XUSB pad controller manages a set of lanes, each of which can be
14 This document defines the device-specific binding for the XUSB pad controller.
/openbmc/linux/drivers/clk/tegra/
H A Dclk-tegra-periph.c207 #define XUSB(_name, _parents, _offset, \ macro
743 …XUSB("xusb_host_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_HOST_SRC, 143, TEGRA_PERIPH_ON_APB…
744 …XUSB("xusb_host_src", mux_clkm_pllp_pllre, CLK_SOURCE_XUSB_HOST_SRC, 143, TEGRA_PERIPH_ON_APB | TE…
745 …XUSB("xusb_falcon_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_FALCON_SRC, 143, TEGRA_PERIPH_NO…
746 …XUSB("xusb_falcon_src", mux_clkm_pllp_pllre, CLK_SOURCE_XUSB_FALCON_SRC, 143, TEGRA_PERIPH_NO_RESE…
747 …XUSB("xusb_fs_src", mux_clkm_48M_pllp_480M, CLK_SOURCE_XUSB_FS_SRC, 143, TEGRA_PERIPH_NO_RESET, te…
748 …XUSB("xusb_ss_src", mux_clkm_pllre_clk32_480M_pllc_ref, CLK_SOURCE_XUSB_SS_SRC, 143, TEGRA_PERIPH_…
749 …XUSB("xusb_ss_src", mux_clkm_pllre_clk32_480M, CLK_SOURCE_XUSB_SS_SRC, 143, TEGRA_PERIPH_NO_RESET,…
753 …XUSB("xusb_dev_src", mux_clkm_pllp_pllc_pllre, CLK_SOURCE_XUSB_DEV_SRC, 95, TEGRA_PERIPH_ON_APB | …
754 …XUSB("xusb_dev_src", mux_clkm_pllp_pllre, CLK_SOURCE_XUSB_DEV_SRC, 95, TEGRA_PERIPH_ON_APB | TEGRA…
/openbmc/linux/Documentation/devicetree/bindings/phy/
H A Dnvidia,tegra186-xusb-padctl.yaml7 title: NVIDIA Tegra186 XUSB pad controller
14 The Tegra XUSB pad controller manages a set of I/O lanes (with differential
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
30 Pads will be represented as children of the top-level XUSB pad controller
35 The Tegra hardware documentation refers to the connection between the XUSB
36 pad controller and the XUSB controller as "ports". This is confusing since
54 - description: XUSB pad controller interrupt
85 subnodes, one for each of the pads exposed by the XUSB pad controller.
222 subnodes, one for each of the ports exposed by the XUSB pad controller.
H A Dnvidia,tegra124-xusb-padctl.yaml7 title: NVIDIA Tegra124 XUSB pad controller
14 The Tegra XUSB pad controller manages a set of I/O lanes (with differential
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
30 Pads will be represented as children of the top-level XUSB pad controller
35 The Tegra hardware documentation refers to the connection between the XUSB
36 pad controller and the XUSB controller as "ports". This is confusing since
58 - description: XUSB pad controller interrupt
82 subnodes, one for each of the pads exposed by the XUSB pad controller.
319 subnodes, one for each of the ports exposed by the XUSB pad controller.
H A Dnvidia,tegra194-xusb-padctl.yaml7 title: NVIDIA Tegra194 XUSB pad controller
14 The Tegra XUSB pad controller manages a set of I/O lanes (with differential
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
30 Pads will be represented as children of the top-level XUSB pad controller
35 The Tegra hardware documentation refers to the connection between the XUSB
36 pad controller and the XUSB controller as "ports". This is confusing since
61 - description: XUSB pad controller interrupt
80 subnodes, one for each of the pads exposed by the XUSB pad controller.
213 subnodes, one for each of the ports exposed by the XUSB pad controller.
H A Dnvidia,tegra210-xusb-padctl.yaml7 title: NVIDIA Tegra210 XUSB pad controller
14 The Tegra XUSB pad controller manages a set of I/O lanes (with differential
23 or high-speed USB (such as UTMI, ULPI and HSIC). The XUSB pad controller
30 Pads will be represented as children of the top-level XUSB pad controller
35 The Tegra hardware documentation refers to the connection between the XUSB
36 pad controller and the XUSB controller as "ports". This is confusing since
56 - description: XUSB pad controller interrupt
80 subnodes, one for each of the pads exposed by the XUSB pad controller.
341 subnodes, one for each of the ports exposed by the XUSB pad controller.
/openbmc/linux/drivers/phy/tegra/
H A DKconfig3 tristate "NVIDIA Tegra XUSB pad controller driver"
/openbmc/u-boot/arch/arm/mach-tegra/tegra114/
H A Dclock.c404 NONE(XUSB),
/openbmc/linux/
H A DMAINTAINERS21249 TEGRA XUSB PADCTL DRIVER