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Searched refs:XOR (Results 1 – 13 of 13) sorted by relevance

/openbmc/bmcweb/redfish-core/include/generated/enums/
H A Dethernet_interface.hpp47 XOR, enumerator
99 {TeamMode::XOR, "XOR"},
/openbmc/qemu/target/rx/
H A Dinsns.decode615 # XOR #imm, rd
617 # XOR dsp[rs].ub, rd
618 # XOR rs, rd
620 # XOR dsp[rs], rd
/openbmc/qemu/docs/specs/
H A Dppc-spapr-hcalls.rst65 of memory (supports overlap of source and destination) and XOR which
/openbmc/qemu/target/hexagon/imported/
H A Dalu.idef44 COND_ALU(A2_pxor,"Rd32=xor(Rs32,Rt32)","Conditionally XOR registers",RdV=RsV^RtV)
336 "logical XOR",{ RdV=RsV^RtV;})
339 "logical XOR with XOR accumulation",{ RxV^=RsV^RtV;})
342 "logical XOR with XOR accumulation",{ RxxV^=RssV^RttV;})
H A Dcompare.idef153 "Predicate XOR",
/openbmc/qemu/docs/
H A Dxbzrle.txt25 The compression format performs a XOR between the previous and current content
/openbmc/libmctp/docs/bindings/
H A Dvendor-ibm-astlpc.md240 3. Incrementally shifting and `XOR`ing data bytes through the reversed
242 4. `XOR`ing the calculated remainder with `2^32 - 1`
/openbmc/qemu/target/sparc/
H A Dinsns.decode244 XOR 10 ..... 0.0011 ..... . ............. @r_r_ri_cc
/openbmc/qemu/target/i386/tcg/
H A Ddecode-new.c.inc1607 [0x30] = X86_OP_ENTRY2(XOR, E,b, G,b, lock),
1608 [0x31] = X86_OP_ENTRY2(XOR, E,v, G,v, lock),
1609 [0x32] = X86_OP_ENTRY2(XOR, G,b, E,b, lock),
1610 [0x33] = X86_OP_ENTRY2(XOR, G,v, E,v, lock),
1611 [0x34] = X86_OP_ENTRY2(XOR, 0,b, I,b, lock), /* AL, Ib */
1612 [0x35] = X86_OP_ENTRY2(XOR, 0,v, I,z, lock), /* rAX, Iz */
H A Demit.c.inc3445 * a XOR, and that is commutative unlike subtraction.
4776 /* special case XOR reg, reg */
/openbmc/qemu/tests/tcg/i386/
H A Dx86.csv4619 "XOR r/m8, imm8","XORB imm8, r/m8","xorb imm8, r/m8","REX 80 /6 ib","N.E.","V","","pseudo64","rw,r"…
4620 "XOR AL, imm8u","XORB imm8u, AL","xorb imm8u, AL","34 ib","V","V","","","rw,r","Y","8"
4621 "XOR r/m8, imm8u","XORB imm8u, r/m8","xorb imm8u, r/m8","80 /6 ib","V","V","","","rw,r","Y","8"
4622 "XOR r/m8, imm8u","XORB imm8u, r/m8","xorb imm8u, r/m8","82 /6 ib","V","N.S.","","","rw,r","Y","8"
4623 "XOR r8, r/m8","XORB r/m8, r8","xorb r/m8, r8","32 /r","V","V","","","rw,r","Y","8"
4624 "XOR r8, r/m8","XORB r/m8, r8","xorb r/m8, r8","REX 32 /r","N.E.","V","","pseudo64","rw,r","Y","8"
4625 "XOR r/m8, r8","XORB r8, r/m8","xorb r8, r/m8","30 /r","V","V","","","rw,r","Y","8"
4626 "XOR r/m8, r8","XORB r8, r/m8","xorb r8, r/m8","REX 30 /r","N.E.","V","","pseudo64","rw,r","Y","8"
4627 "XOR EAX, imm32","XORL imm32, EAX","xorl imm32, EAX","35 id","V","V","","operand32","rw,r","Y","32"
4628 "XOR r/m32, imm32","XORL imm32, r/m32","xorl imm32, r/m32","81 /6 id","V","V","","operand32","rw,r"…
[all …]
/openbmc/openbmc/poky/meta/recipes-bsp/v86d/v86d/
H A DUpdate-x86emu-from-X.org.patch4804 DECODE_PRINTF("XOR\tEAX,");
4809 DECODE_PRINTF("XOR\tAX,");
17655 Implements the XOR instruction and side effects.
17684 Implements the XOR instruction and side effects.
17713 Implements the XOR instruction and side effects.
/openbmc/qemu/target/hexagon/imported/mmvec/
H A Dext.idef1670 ITERATOR_INSN_ANY_SLOT(16,vxor,"Vd32=vxor(Vu32,Vv32)", "Vector Logical XOR", VdV.uh[i] = VuV.uh[…