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Searched refs:XCHAL_DATARAM0_BANKS (Results 1 – 4 of 4) sorted by relevance

/openbmc/linux/arch/xtensa/variants/de212/include/variant/
H A Dcore.h301 #define XCHAL_DATARAM0_BANKS 1 /* number of banks */ macro
/openbmc/u-boot/arch/xtensa/include/asm/arch-de212/
H A Dcore.h279 #define XCHAL_DATARAM0_BANKS 1 /* number of banks */ macro
/openbmc/qemu/target/xtensa/core-de212/
H A Dcore-isa.h307 #define XCHAL_DATARAM0_BANKS 1 /* number of banks */ macro
/openbmc/qemu/target/xtensa/core-sample_controller/
H A Dcore-isa.h325 #define XCHAL_DATARAM0_BANKS 1 /* number of banks */ macro