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Searched refs:WR2PRE (Results 1 – 1 of 1) sorted by relevance

/openbmc/u-boot/arch/arm/mach-sunxi/
H A Ddram_sun9i.c518 #define WR2PRE (MCTL_BL/2 + CWL + tWTR) in mctl_channel_init() macro
533 writel((MCTL_DIV2(WR2PRE) << 24) | (MCTL_DIV2(tFAW) << 16) | in mctl_channel_init()