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Searched refs:WB_EC_CONFIG__WBSCL_LB_MEM_PWR_MODE_SEL_MASK (Results 1 – 6 of 6) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dce/
H A Ddce_10_0_sh_mask.h14562 #define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_MODE_SEL_MASK 0x600 macro
H A Ddce_11_0_sh_mask.h14558 #define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_MODE_SEL_MASK 0x600 macro
H A Ddce_11_2_sh_mask.h15176 #define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_MODE_SEL_MASK 0x3000 macro
H A Ddce_12_0_sh_mask.h4352 #define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_MODE_SEL_MASK … macro
/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_1_0_sh_mask.h5660 #define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_MODE_SEL_MASK … macro
H A Ddcn_2_0_0_sh_mask.h5924 #define WB_EC_CONFIG__WBSCL_LB_MEM_PWR_MODE_SEL_MASK … macro