1 // SPDX-License-Identifier: GPL-2.0
2 /* DSA driver for:
3 * Vitesse VSC7385 SparX-G5 5+1-port Integrated Gigabit Ethernet Switch
4 * Vitesse VSC7388 SparX-G8 8-port Integrated Gigabit Ethernet Switch
5 * Vitesse VSC7395 SparX-G5e 5+1-port Integrated Gigabit Ethernet Switch
6 * Vitesse VSC7398 SparX-G8e 8-port Integrated Gigabit Ethernet Switch
7 *
8 * These switches have a built-in 8051 CPU and can download and execute a
9 * firmware in this CPU. They can also be configured to use an external CPU
10 * handling the switch in a memory-mapped manner by connecting to that external
11 * CPU's memory bus.
12 *
13 * Copyright (C) 2018 Linus Wallej <linus.walleij@linaro.org>
14 * Includes portions of code from the firmware uploader by:
15 * Copyright (C) 2009 Gabor Juhos <juhosg@openwrt.org>
16 */
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/device.h>
20 #include <linux/iopoll.h>
21 #include <linux/of.h>
22 #include <linux/of_mdio.h>
23 #include <linux/bitops.h>
24 #include <linux/if_bridge.h>
25 #include <linux/etherdevice.h>
26 #include <linux/gpio/consumer.h>
27 #include <linux/gpio/driver.h>
28 #include <linux/random.h>
29 #include <net/dsa.h>
30
31 #include "vitesse-vsc73xx.h"
32
33 #define VSC73XX_BLOCK_MAC 0x1 /* Subblocks 0-4, 6 (CPU port) */
34 #define VSC73XX_BLOCK_ANALYZER 0x2 /* Only subblock 0 */
35 #define VSC73XX_BLOCK_MII 0x3 /* Subblocks 0 and 1 */
36 #define VSC73XX_BLOCK_MEMINIT 0x3 /* Only subblock 2 */
37 #define VSC73XX_BLOCK_CAPTURE 0x4 /* Subblocks 0-4, 6, 7 */
38 #define VSC73XX_BLOCK_ARBITER 0x5 /* Only subblock 0 */
39 #define VSC73XX_BLOCK_SYSTEM 0x7 /* Only subblock 0 */
40
41 /* MII Block subblock */
42 #define VSC73XX_BLOCK_MII_INTERNAL 0x0 /* Internal MDIO subblock */
43 #define VSC73XX_BLOCK_MII_EXTERNAL 0x1 /* External MDIO subblock */
44
45 #define CPU_PORT 6 /* CPU port */
46
47 /* MAC Block registers */
48 #define VSC73XX_MAC_CFG 0x00
49 #define VSC73XX_MACHDXGAP 0x02
50 #define VSC73XX_FCCONF 0x04
51 #define VSC73XX_FCMACHI 0x08
52 #define VSC73XX_FCMACLO 0x0c
53 #define VSC73XX_MAXLEN 0x10
54 #define VSC73XX_ADVPORTM 0x19
55 #define VSC73XX_TXUPDCFG 0x24
56 #define VSC73XX_TXQ_SELECT_CFG 0x28
57 #define VSC73XX_RXOCT 0x50
58 #define VSC73XX_TXOCT 0x51
59 #define VSC73XX_C_RX0 0x52
60 #define VSC73XX_C_RX1 0x53
61 #define VSC73XX_C_RX2 0x54
62 #define VSC73XX_C_TX0 0x55
63 #define VSC73XX_C_TX1 0x56
64 #define VSC73XX_C_TX2 0x57
65 #define VSC73XX_C_CFG 0x58
66 #define VSC73XX_CAT_DROP 0x6e
67 #define VSC73XX_CAT_PR_MISC_L2 0x6f
68 #define VSC73XX_CAT_PR_USR_PRIO 0x75
69 #define VSC73XX_Q_MISC_CONF 0xdf
70
71 /* MAC_CFG register bits */
72 #define VSC73XX_MAC_CFG_WEXC_DIS BIT(31)
73 #define VSC73XX_MAC_CFG_PORT_RST BIT(29)
74 #define VSC73XX_MAC_CFG_TX_EN BIT(28)
75 #define VSC73XX_MAC_CFG_SEED_LOAD BIT(27)
76 #define VSC73XX_MAC_CFG_SEED_MASK GENMASK(26, 19)
77 #define VSC73XX_MAC_CFG_SEED_OFFSET 19
78 #define VSC73XX_MAC_CFG_FDX BIT(18)
79 #define VSC73XX_MAC_CFG_GIGA_MODE BIT(17)
80 #define VSC73XX_MAC_CFG_RX_EN BIT(16)
81 #define VSC73XX_MAC_CFG_VLAN_DBLAWR BIT(15)
82 #define VSC73XX_MAC_CFG_VLAN_AWR BIT(14)
83 #define VSC73XX_MAC_CFG_100_BASE_T BIT(13) /* Not in manual */
84 #define VSC73XX_MAC_CFG_TX_IPG_MASK GENMASK(10, 6)
85 #define VSC73XX_MAC_CFG_TX_IPG_OFFSET 6
86 #define VSC73XX_MAC_CFG_TX_IPG_1000M (6 << VSC73XX_MAC_CFG_TX_IPG_OFFSET)
87 #define VSC73XX_MAC_CFG_TX_IPG_100_10M (17 << VSC73XX_MAC_CFG_TX_IPG_OFFSET)
88 #define VSC73XX_MAC_CFG_MAC_RX_RST BIT(5)
89 #define VSC73XX_MAC_CFG_MAC_TX_RST BIT(4)
90 #define VSC73XX_MAC_CFG_CLK_SEL_MASK GENMASK(2, 0)
91 #define VSC73XX_MAC_CFG_CLK_SEL_OFFSET 0
92 #define VSC73XX_MAC_CFG_CLK_SEL_1000M 1
93 #define VSC73XX_MAC_CFG_CLK_SEL_100M 2
94 #define VSC73XX_MAC_CFG_CLK_SEL_10M 3
95 #define VSC73XX_MAC_CFG_CLK_SEL_EXT 4
96
97 #define VSC73XX_MAC_CFG_1000M_F_PHY (VSC73XX_MAC_CFG_FDX | \
98 VSC73XX_MAC_CFG_GIGA_MODE | \
99 VSC73XX_MAC_CFG_TX_IPG_1000M | \
100 VSC73XX_MAC_CFG_CLK_SEL_EXT)
101 #define VSC73XX_MAC_CFG_100_10M_F_PHY (VSC73XX_MAC_CFG_FDX | \
102 VSC73XX_MAC_CFG_TX_IPG_100_10M | \
103 VSC73XX_MAC_CFG_CLK_SEL_EXT)
104 #define VSC73XX_MAC_CFG_100_10M_H_PHY (VSC73XX_MAC_CFG_TX_IPG_100_10M | \
105 VSC73XX_MAC_CFG_CLK_SEL_EXT)
106 #define VSC73XX_MAC_CFG_1000M_F_RGMII (VSC73XX_MAC_CFG_FDX | \
107 VSC73XX_MAC_CFG_GIGA_MODE | \
108 VSC73XX_MAC_CFG_TX_IPG_1000M | \
109 VSC73XX_MAC_CFG_CLK_SEL_1000M)
110 #define VSC73XX_MAC_CFG_RESET (VSC73XX_MAC_CFG_PORT_RST | \
111 VSC73XX_MAC_CFG_MAC_RX_RST | \
112 VSC73XX_MAC_CFG_MAC_TX_RST)
113
114 /* Flow control register bits */
115 #define VSC73XX_FCCONF_ZERO_PAUSE_EN BIT(17)
116 #define VSC73XX_FCCONF_FLOW_CTRL_OBEY BIT(16)
117 #define VSC73XX_FCCONF_PAUSE_VAL_MASK GENMASK(15, 0)
118
119 /* ADVPORTM advanced port setup register bits */
120 #define VSC73XX_ADVPORTM_IFG_PPM BIT(7)
121 #define VSC73XX_ADVPORTM_EXC_COL_CONT BIT(6)
122 #define VSC73XX_ADVPORTM_EXT_PORT BIT(5)
123 #define VSC73XX_ADVPORTM_INV_GTX BIT(4)
124 #define VSC73XX_ADVPORTM_ENA_GTX BIT(3)
125 #define VSC73XX_ADVPORTM_DDR_MODE BIT(2)
126 #define VSC73XX_ADVPORTM_IO_LOOPBACK BIT(1)
127 #define VSC73XX_ADVPORTM_HOST_LOOPBACK BIT(0)
128
129 /* CAT_DROP categorizer frame dropping register bits */
130 #define VSC73XX_CAT_DROP_DROP_MC_SMAC_ENA BIT(6)
131 #define VSC73XX_CAT_DROP_FWD_CTRL_ENA BIT(4)
132 #define VSC73XX_CAT_DROP_FWD_PAUSE_ENA BIT(3)
133 #define VSC73XX_CAT_DROP_UNTAGGED_ENA BIT(2)
134 #define VSC73XX_CAT_DROP_TAGGED_ENA BIT(1)
135 #define VSC73XX_CAT_DROP_NULL_MAC_ENA BIT(0)
136
137 #define VSC73XX_Q_MISC_CONF_EXTENT_MEM BIT(31)
138 #define VSC73XX_Q_MISC_CONF_EARLY_TX_MASK GENMASK(4, 1)
139 #define VSC73XX_Q_MISC_CONF_EARLY_TX_512 (1 << 1)
140 #define VSC73XX_Q_MISC_CONF_MAC_PAUSE_MODE BIT(0)
141
142 /* Frame analyzer block 2 registers */
143 #define VSC73XX_STORMLIMIT 0x02
144 #define VSC73XX_ADVLEARN 0x03
145 #define VSC73XX_IFLODMSK 0x04
146 #define VSC73XX_VLANMASK 0x05
147 #define VSC73XX_MACHDATA 0x06
148 #define VSC73XX_MACLDATA 0x07
149 #define VSC73XX_ANMOVED 0x08
150 #define VSC73XX_ANAGEFIL 0x09
151 #define VSC73XX_ANEVENTS 0x0a
152 #define VSC73XX_ANCNTMASK 0x0b
153 #define VSC73XX_ANCNTVAL 0x0c
154 #define VSC73XX_LEARNMASK 0x0d
155 #define VSC73XX_UFLODMASK 0x0e
156 #define VSC73XX_MFLODMASK 0x0f
157 #define VSC73XX_RECVMASK 0x10
158 #define VSC73XX_AGGRCTRL 0x20
159 #define VSC73XX_AGGRMSKS 0x30 /* Until 0x3f */
160 #define VSC73XX_DSTMASKS 0x40 /* Until 0x7f */
161 #define VSC73XX_SRCMASKS 0x80 /* Until 0x87 */
162 #define VSC73XX_CAPENAB 0xa0
163 #define VSC73XX_MACACCESS 0xb0
164 #define VSC73XX_IPMCACCESS 0xb1
165 #define VSC73XX_MACTINDX 0xc0
166 #define VSC73XX_VLANACCESS 0xd0
167 #define VSC73XX_VLANTIDX 0xe0
168 #define VSC73XX_AGENCTRL 0xf0
169 #define VSC73XX_CAPRST 0xff
170
171 #define VSC73XX_MACACCESS_CPU_COPY BIT(14)
172 #define VSC73XX_MACACCESS_FWD_KILL BIT(13)
173 #define VSC73XX_MACACCESS_IGNORE_VLAN BIT(12)
174 #define VSC73XX_MACACCESS_AGED_FLAG BIT(11)
175 #define VSC73XX_MACACCESS_VALID BIT(10)
176 #define VSC73XX_MACACCESS_LOCKED BIT(9)
177 #define VSC73XX_MACACCESS_DEST_IDX_MASK GENMASK(8, 3)
178 #define VSC73XX_MACACCESS_CMD_MASK GENMASK(2, 0)
179 #define VSC73XX_MACACCESS_CMD_IDLE 0
180 #define VSC73XX_MACACCESS_CMD_LEARN 1
181 #define VSC73XX_MACACCESS_CMD_FORGET 2
182 #define VSC73XX_MACACCESS_CMD_AGE_TABLE 3
183 #define VSC73XX_MACACCESS_CMD_FLUSH_TABLE 4
184 #define VSC73XX_MACACCESS_CMD_CLEAR_TABLE 5
185 #define VSC73XX_MACACCESS_CMD_READ_ENTRY 6
186 #define VSC73XX_MACACCESS_CMD_WRITE_ENTRY 7
187
188 #define VSC73XX_VLANACCESS_LEARN_DISABLED BIT(30)
189 #define VSC73XX_VLANACCESS_VLAN_MIRROR BIT(29)
190 #define VSC73XX_VLANACCESS_VLAN_SRC_CHECK BIT(28)
191 #define VSC73XX_VLANACCESS_VLAN_PORT_MASK GENMASK(9, 2)
192 #define VSC73XX_VLANACCESS_VLAN_TBL_CMD_MASK GENMASK(2, 0)
193 #define VSC73XX_VLANACCESS_VLAN_TBL_CMD_IDLE 0
194 #define VSC73XX_VLANACCESS_VLAN_TBL_CMD_READ_ENTRY 1
195 #define VSC73XX_VLANACCESS_VLAN_TBL_CMD_WRITE_ENTRY 2
196 #define VSC73XX_VLANACCESS_VLAN_TBL_CMD_CLEAR_TABLE 3
197
198 /* MII block 3 registers */
199 #define VSC73XX_MII_STAT 0x0
200 #define VSC73XX_MII_CMD 0x1
201 #define VSC73XX_MII_DATA 0x2
202
203 #define VSC73XX_MII_STAT_BUSY BIT(3)
204
205 /* Arbiter block 5 registers */
206 #define VSC73XX_ARBEMPTY 0x0c
207 #define VSC73XX_ARBDISC 0x0e
208 #define VSC73XX_SBACKWDROP 0x12
209 #define VSC73XX_DBACKWDROP 0x13
210 #define VSC73XX_ARBBURSTPROB 0x15
211
212 /* System block 7 registers */
213 #define VSC73XX_ICPU_SIPAD 0x01
214 #define VSC73XX_GMIIDELAY 0x05
215 #define VSC73XX_ICPU_CTRL 0x10
216 #define VSC73XX_ICPU_ADDR 0x11
217 #define VSC73XX_ICPU_SRAM 0x12
218 #define VSC73XX_HWSEM 0x13
219 #define VSC73XX_GLORESET 0x14
220 #define VSC73XX_ICPU_MBOX_VAL 0x15
221 #define VSC73XX_ICPU_MBOX_SET 0x16
222 #define VSC73XX_ICPU_MBOX_CLR 0x17
223 #define VSC73XX_CHIPID 0x18
224 #define VSC73XX_GPIO 0x34
225
226 #define VSC73XX_GMIIDELAY_GMII0_GTXDELAY_NONE 0
227 #define VSC73XX_GMIIDELAY_GMII0_GTXDELAY_1_4_NS 1
228 #define VSC73XX_GMIIDELAY_GMII0_GTXDELAY_1_7_NS 2
229 #define VSC73XX_GMIIDELAY_GMII0_GTXDELAY_2_0_NS 3
230
231 #define VSC73XX_GMIIDELAY_GMII0_RXDELAY_NONE (0 << 4)
232 #define VSC73XX_GMIIDELAY_GMII0_RXDELAY_1_4_NS (1 << 4)
233 #define VSC73XX_GMIIDELAY_GMII0_RXDELAY_1_7_NS (2 << 4)
234 #define VSC73XX_GMIIDELAY_GMII0_RXDELAY_2_0_NS (3 << 4)
235
236 #define VSC73XX_ICPU_CTRL_WATCHDOG_RST BIT(31)
237 #define VSC73XX_ICPU_CTRL_CLK_DIV_MASK GENMASK(12, 8)
238 #define VSC73XX_ICPU_CTRL_SRST_HOLD BIT(7)
239 #define VSC73XX_ICPU_CTRL_ICPU_PI_EN BIT(6)
240 #define VSC73XX_ICPU_CTRL_BOOT_EN BIT(3)
241 #define VSC73XX_ICPU_CTRL_EXT_ACC_EN BIT(2)
242 #define VSC73XX_ICPU_CTRL_CLK_EN BIT(1)
243 #define VSC73XX_ICPU_CTRL_SRST BIT(0)
244
245 #define VSC73XX_CHIPID_ID_SHIFT 12
246 #define VSC73XX_CHIPID_ID_MASK 0xffff
247 #define VSC73XX_CHIPID_REV_SHIFT 28
248 #define VSC73XX_CHIPID_REV_MASK 0xf
249 #define VSC73XX_CHIPID_ID_7385 0x7385
250 #define VSC73XX_CHIPID_ID_7388 0x7388
251 #define VSC73XX_CHIPID_ID_7395 0x7395
252 #define VSC73XX_CHIPID_ID_7398 0x7398
253
254 #define VSC73XX_GLORESET_STROBE BIT(4)
255 #define VSC73XX_GLORESET_ICPU_LOCK BIT(3)
256 #define VSC73XX_GLORESET_MEM_LOCK BIT(2)
257 #define VSC73XX_GLORESET_PHY_RESET BIT(1)
258 #define VSC73XX_GLORESET_MASTER_RESET BIT(0)
259
260 #define VSC7385_CLOCK_DELAY ((3 << 4) | 3)
261 #define VSC7385_CLOCK_DELAY_MASK ((3 << 4) | 3)
262
263 #define VSC73XX_ICPU_CTRL_STOP (VSC73XX_ICPU_CTRL_SRST_HOLD | \
264 VSC73XX_ICPU_CTRL_BOOT_EN | \
265 VSC73XX_ICPU_CTRL_EXT_ACC_EN)
266
267 #define VSC73XX_ICPU_CTRL_START (VSC73XX_ICPU_CTRL_CLK_DIV | \
268 VSC73XX_ICPU_CTRL_BOOT_EN | \
269 VSC73XX_ICPU_CTRL_CLK_EN | \
270 VSC73XX_ICPU_CTRL_SRST)
271
272 #define IS_7385(a) ((a)->chipid == VSC73XX_CHIPID_ID_7385)
273 #define IS_7388(a) ((a)->chipid == VSC73XX_CHIPID_ID_7388)
274 #define IS_7395(a) ((a)->chipid == VSC73XX_CHIPID_ID_7395)
275 #define IS_7398(a) ((a)->chipid == VSC73XX_CHIPID_ID_7398)
276 #define IS_739X(a) (IS_7395(a) || IS_7398(a))
277
278 #define VSC73XX_POLL_SLEEP_US 1000
279 #define VSC73XX_MDIO_POLL_SLEEP_US 5
280 #define VSC73XX_POLL_TIMEOUT_US 10000
281
282 struct vsc73xx_counter {
283 u8 counter;
284 const char *name;
285 };
286
287 /* Counters are named according to the MIB standards where applicable.
288 * Some counters are custom, non-standard. The standard counters are
289 * named in accordance with RFC2819, RFC2021 and IEEE Std 802.3-2002 Annex
290 * 30A Counters.
291 */
292 static const struct vsc73xx_counter vsc73xx_rx_counters[] = {
293 { 0, "RxEtherStatsPkts" },
294 { 1, "RxBroadcast+MulticastPkts" }, /* non-standard counter */
295 { 2, "RxTotalErrorPackets" }, /* non-standard counter */
296 { 3, "RxEtherStatsBroadcastPkts" },
297 { 4, "RxEtherStatsMulticastPkts" },
298 { 5, "RxEtherStatsPkts64Octets" },
299 { 6, "RxEtherStatsPkts65to127Octets" },
300 { 7, "RxEtherStatsPkts128to255Octets" },
301 { 8, "RxEtherStatsPkts256to511Octets" },
302 { 9, "RxEtherStatsPkts512to1023Octets" },
303 { 10, "RxEtherStatsPkts1024to1518Octets" },
304 { 11, "RxJumboFrames" }, /* non-standard counter */
305 { 12, "RxaPauseMACControlFramesTransmitted" },
306 { 13, "RxFIFODrops" }, /* non-standard counter */
307 { 14, "RxBackwardDrops" }, /* non-standard counter */
308 { 15, "RxClassifierDrops" }, /* non-standard counter */
309 { 16, "RxEtherStatsCRCAlignErrors" },
310 { 17, "RxEtherStatsUndersizePkts" },
311 { 18, "RxEtherStatsOversizePkts" },
312 { 19, "RxEtherStatsFragments" },
313 { 20, "RxEtherStatsJabbers" },
314 { 21, "RxaMACControlFramesReceived" },
315 /* 22-24 are undefined */
316 { 25, "RxaFramesReceivedOK" },
317 { 26, "RxQoSClass0" }, /* non-standard counter */
318 { 27, "RxQoSClass1" }, /* non-standard counter */
319 { 28, "RxQoSClass2" }, /* non-standard counter */
320 { 29, "RxQoSClass3" }, /* non-standard counter */
321 };
322
323 static const struct vsc73xx_counter vsc73xx_tx_counters[] = {
324 { 0, "TxEtherStatsPkts" },
325 { 1, "TxBroadcast+MulticastPkts" }, /* non-standard counter */
326 { 2, "TxTotalErrorPackets" }, /* non-standard counter */
327 { 3, "TxEtherStatsBroadcastPkts" },
328 { 4, "TxEtherStatsMulticastPkts" },
329 { 5, "TxEtherStatsPkts64Octets" },
330 { 6, "TxEtherStatsPkts65to127Octets" },
331 { 7, "TxEtherStatsPkts128to255Octets" },
332 { 8, "TxEtherStatsPkts256to511Octets" },
333 { 9, "TxEtherStatsPkts512to1023Octets" },
334 { 10, "TxEtherStatsPkts1024to1518Octets" },
335 { 11, "TxJumboFrames" }, /* non-standard counter */
336 { 12, "TxaPauseMACControlFramesTransmitted" },
337 { 13, "TxFIFODrops" }, /* non-standard counter */
338 { 14, "TxDrops" }, /* non-standard counter */
339 { 15, "TxEtherStatsCollisions" },
340 { 16, "TxEtherStatsCRCAlignErrors" },
341 { 17, "TxEtherStatsUndersizePkts" },
342 { 18, "TxEtherStatsOversizePkts" },
343 { 19, "TxEtherStatsFragments" },
344 { 20, "TxEtherStatsJabbers" },
345 /* 21-24 are undefined */
346 { 25, "TxaFramesReceivedOK" },
347 { 26, "TxQoSClass0" }, /* non-standard counter */
348 { 27, "TxQoSClass1" }, /* non-standard counter */
349 { 28, "TxQoSClass2" }, /* non-standard counter */
350 { 29, "TxQoSClass3" }, /* non-standard counter */
351 };
352
vsc73xx_is_addr_valid(u8 block,u8 subblock)353 int vsc73xx_is_addr_valid(u8 block, u8 subblock)
354 {
355 switch (block) {
356 case VSC73XX_BLOCK_MAC:
357 switch (subblock) {
358 case 0 ... 4:
359 case 6:
360 return 1;
361 }
362 break;
363
364 case VSC73XX_BLOCK_ANALYZER:
365 case VSC73XX_BLOCK_SYSTEM:
366 switch (subblock) {
367 case 0:
368 return 1;
369 }
370 break;
371
372 case VSC73XX_BLOCK_MII:
373 case VSC73XX_BLOCK_ARBITER:
374 switch (subblock) {
375 case 0 ... 1:
376 return 1;
377 }
378 break;
379 case VSC73XX_BLOCK_CAPTURE:
380 switch (subblock) {
381 case 0 ... 4:
382 case 6 ... 7:
383 return 1;
384 }
385 break;
386 }
387
388 return 0;
389 }
390 EXPORT_SYMBOL(vsc73xx_is_addr_valid);
391
vsc73xx_read(struct vsc73xx * vsc,u8 block,u8 subblock,u8 reg,u32 * val)392 static int vsc73xx_read(struct vsc73xx *vsc, u8 block, u8 subblock, u8 reg,
393 u32 *val)
394 {
395 return vsc->ops->read(vsc, block, subblock, reg, val);
396 }
397
vsc73xx_write(struct vsc73xx * vsc,u8 block,u8 subblock,u8 reg,u32 val)398 static int vsc73xx_write(struct vsc73xx *vsc, u8 block, u8 subblock, u8 reg,
399 u32 val)
400 {
401 return vsc->ops->write(vsc, block, subblock, reg, val);
402 }
403
vsc73xx_update_bits(struct vsc73xx * vsc,u8 block,u8 subblock,u8 reg,u32 mask,u32 val)404 static int vsc73xx_update_bits(struct vsc73xx *vsc, u8 block, u8 subblock,
405 u8 reg, u32 mask, u32 val)
406 {
407 u32 tmp, orig;
408 int ret;
409
410 /* Same read-modify-write algorithm as e.g. regmap */
411 ret = vsc73xx_read(vsc, block, subblock, reg, &orig);
412 if (ret)
413 return ret;
414 tmp = orig & ~mask;
415 tmp |= val & mask;
416 return vsc73xx_write(vsc, block, subblock, reg, tmp);
417 }
418
vsc73xx_detect(struct vsc73xx * vsc)419 static int vsc73xx_detect(struct vsc73xx *vsc)
420 {
421 bool icpu_si_boot_en;
422 bool icpu_pi_en;
423 u32 val;
424 u32 rev;
425 int ret;
426 u32 id;
427
428 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_SYSTEM, 0,
429 VSC73XX_ICPU_MBOX_VAL, &val);
430 if (ret) {
431 dev_err(vsc->dev, "unable to read mailbox (%d)\n", ret);
432 return ret;
433 }
434
435 if (val == 0xffffffff) {
436 dev_info(vsc->dev, "chip seems dead.\n");
437 return -EAGAIN;
438 }
439
440 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_SYSTEM, 0,
441 VSC73XX_CHIPID, &val);
442 if (ret) {
443 dev_err(vsc->dev, "unable to read chip id (%d)\n", ret);
444 return ret;
445 }
446
447 id = (val >> VSC73XX_CHIPID_ID_SHIFT) &
448 VSC73XX_CHIPID_ID_MASK;
449 switch (id) {
450 case VSC73XX_CHIPID_ID_7385:
451 case VSC73XX_CHIPID_ID_7388:
452 case VSC73XX_CHIPID_ID_7395:
453 case VSC73XX_CHIPID_ID_7398:
454 break;
455 default:
456 dev_err(vsc->dev, "unsupported chip, id=%04x\n", id);
457 return -ENODEV;
458 }
459
460 vsc->chipid = id;
461 rev = (val >> VSC73XX_CHIPID_REV_SHIFT) &
462 VSC73XX_CHIPID_REV_MASK;
463 dev_info(vsc->dev, "VSC%04X (rev: %d) switch found\n", id, rev);
464
465 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_SYSTEM, 0,
466 VSC73XX_ICPU_CTRL, &val);
467 if (ret) {
468 dev_err(vsc->dev, "unable to read iCPU control\n");
469 return ret;
470 }
471
472 /* The iCPU can always be used but can boot in different ways.
473 * If it is initially disabled and has no external memory,
474 * we are in control and can do whatever we like, else we
475 * are probably in trouble (we need some way to communicate
476 * with the running firmware) so we bail out for now.
477 */
478 icpu_pi_en = !!(val & VSC73XX_ICPU_CTRL_ICPU_PI_EN);
479 icpu_si_boot_en = !!(val & VSC73XX_ICPU_CTRL_BOOT_EN);
480 if (icpu_si_boot_en && icpu_pi_en) {
481 dev_err(vsc->dev,
482 "iCPU enabled boots from SI, has external memory\n");
483 dev_err(vsc->dev, "no idea how to deal with this\n");
484 return -ENODEV;
485 }
486 if (icpu_si_boot_en && !icpu_pi_en) {
487 dev_err(vsc->dev,
488 "iCPU enabled boots from PI/SI, no external memory\n");
489 return -EAGAIN;
490 }
491 if (!icpu_si_boot_en && icpu_pi_en) {
492 dev_err(vsc->dev,
493 "iCPU enabled, boots from PI external memory\n");
494 dev_err(vsc->dev, "no idea how to deal with this\n");
495 return -ENODEV;
496 }
497 /* !icpu_si_boot_en && !cpu_pi_en */
498 dev_info(vsc->dev, "iCPU disabled, no external memory\n");
499
500 return 0;
501 }
502
vsc73xx_mdio_busy_check(struct vsc73xx * vsc)503 static int vsc73xx_mdio_busy_check(struct vsc73xx *vsc)
504 {
505 int ret, err;
506 u32 val;
507
508 ret = read_poll_timeout(vsc73xx_read, err,
509 err < 0 || !(val & VSC73XX_MII_STAT_BUSY),
510 VSC73XX_MDIO_POLL_SLEEP_US,
511 VSC73XX_POLL_TIMEOUT_US, false, vsc,
512 VSC73XX_BLOCK_MII, VSC73XX_BLOCK_MII_INTERNAL,
513 VSC73XX_MII_STAT, &val);
514 if (ret)
515 return ret;
516 return err;
517 }
518
vsc73xx_phy_read(struct dsa_switch * ds,int phy,int regnum)519 static int vsc73xx_phy_read(struct dsa_switch *ds, int phy, int regnum)
520 {
521 struct vsc73xx *vsc = ds->priv;
522 u32 cmd;
523 u32 val;
524 int ret;
525
526 ret = vsc73xx_mdio_busy_check(vsc);
527 if (ret)
528 return ret;
529
530 /* Setting bit 26 means "read" */
531 cmd = BIT(26) | (phy << 21) | (regnum << 16);
532 ret = vsc73xx_write(vsc, VSC73XX_BLOCK_MII, 0, 1, cmd);
533 if (ret)
534 return ret;
535
536 ret = vsc73xx_mdio_busy_check(vsc);
537 if (ret)
538 return ret;
539
540 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_MII, 0, 2, &val);
541 if (ret)
542 return ret;
543 if (val & BIT(16)) {
544 dev_err(vsc->dev, "reading reg %02x from phy%d failed\n",
545 regnum, phy);
546 return -EIO;
547 }
548 val &= 0xFFFFU;
549
550 dev_dbg(vsc->dev, "read reg %02x from phy%d = %04x\n",
551 regnum, phy, val);
552
553 return val;
554 }
555
vsc73xx_phy_write(struct dsa_switch * ds,int phy,int regnum,u16 val)556 static int vsc73xx_phy_write(struct dsa_switch *ds, int phy, int regnum,
557 u16 val)
558 {
559 struct vsc73xx *vsc = ds->priv;
560 u32 cmd;
561 int ret;
562
563 ret = vsc73xx_mdio_busy_check(vsc);
564 if (ret)
565 return ret;
566
567 /* It was found through tedious experiments that this router
568 * chip really hates to have it's PHYs reset. They
569 * never recover if that happens: autonegotiation stops
570 * working after a reset. Just filter out this command.
571 * (Resetting the whole chip is OK.)
572 */
573 if (regnum == 0 && (val & BIT(15))) {
574 dev_info(vsc->dev, "reset PHY - disallowed\n");
575 return 0;
576 }
577
578 cmd = (phy << 21) | (regnum << 16) | val;
579 ret = vsc73xx_write(vsc, VSC73XX_BLOCK_MII, 0, 1, cmd);
580 if (ret)
581 return ret;
582
583 dev_dbg(vsc->dev, "write %04x to reg %02x in phy%d\n",
584 val, regnum, phy);
585 return 0;
586 }
587
vsc73xx_get_tag_protocol(struct dsa_switch * ds,int port,enum dsa_tag_protocol mp)588 static enum dsa_tag_protocol vsc73xx_get_tag_protocol(struct dsa_switch *ds,
589 int port,
590 enum dsa_tag_protocol mp)
591 {
592 /* The switch internally uses a 8 byte header with length,
593 * source port, tag, LPA and priority. This is supposedly
594 * only accessible when operating the switch using the internal
595 * CPU or with an external CPU mapping the device in, but not
596 * when operating the switch over SPI and putting frames in/out
597 * on port 6 (the CPU port). So far we must assume that we
598 * cannot access the tag. (See "Internal frame header" section
599 * 3.9.1 in the manual.)
600 */
601 return DSA_TAG_PROTO_NONE;
602 }
603
vsc73xx_setup(struct dsa_switch * ds)604 static int vsc73xx_setup(struct dsa_switch *ds)
605 {
606 struct vsc73xx *vsc = ds->priv;
607 int i;
608
609 dev_info(vsc->dev, "set up the switch\n");
610
611 /* Issue RESET */
612 vsc73xx_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, VSC73XX_GLORESET,
613 VSC73XX_GLORESET_MASTER_RESET);
614 usleep_range(125, 200);
615
616 /* Initialize memory, initialize RAM bank 0..15 except 6 and 7
617 * This sequence appears in the
618 * VSC7385 SparX-G5 datasheet section 6.6.1
619 * VSC7395 SparX-G5e datasheet section 6.6.1
620 * "initialization sequence".
621 * No explanation is given to the 0x1010400 magic number.
622 */
623 for (i = 0; i <= 15; i++) {
624 if (i != 6 && i != 7) {
625 vsc73xx_write(vsc, VSC73XX_BLOCK_MEMINIT,
626 2,
627 0, 0x1010400 + i);
628 mdelay(1);
629 }
630 }
631 mdelay(30);
632
633 /* Clear MAC table */
634 vsc73xx_write(vsc, VSC73XX_BLOCK_ANALYZER, 0,
635 VSC73XX_MACACCESS,
636 VSC73XX_MACACCESS_CMD_CLEAR_TABLE);
637
638 /* Clear VLAN table */
639 vsc73xx_write(vsc, VSC73XX_BLOCK_ANALYZER, 0,
640 VSC73XX_VLANACCESS,
641 VSC73XX_VLANACCESS_VLAN_TBL_CMD_CLEAR_TABLE);
642
643 msleep(40);
644
645 /* Use 20KiB buffers on all ports on VSC7395
646 * The VSC7385 has 16KiB buffers and that is the
647 * default if we don't set this up explicitly.
648 * Port "31" is "all ports".
649 */
650 if (IS_739X(vsc))
651 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 0x1f,
652 VSC73XX_Q_MISC_CONF,
653 VSC73XX_Q_MISC_CONF_EXTENT_MEM);
654
655 /* Put all ports into reset until enabled */
656 for (i = 0; i < 7; i++) {
657 if (i == 5)
658 continue;
659 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, 4,
660 VSC73XX_MAC_CFG, VSC73XX_MAC_CFG_RESET);
661 }
662
663 /* MII delay, set both GTX and RX delay to 2 ns */
664 vsc73xx_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, VSC73XX_GMIIDELAY,
665 VSC73XX_GMIIDELAY_GMII0_GTXDELAY_2_0_NS |
666 VSC73XX_GMIIDELAY_GMII0_RXDELAY_2_0_NS);
667 /* Enable reception of frames on all ports */
668 vsc73xx_write(vsc, VSC73XX_BLOCK_ANALYZER, 0, VSC73XX_RECVMASK,
669 0x5f);
670 /* IP multicast flood mask (table 144) */
671 vsc73xx_write(vsc, VSC73XX_BLOCK_ANALYZER, 0, VSC73XX_IFLODMSK,
672 0xff);
673
674 mdelay(50);
675
676 /* Release reset from the internal PHYs */
677 vsc73xx_write(vsc, VSC73XX_BLOCK_SYSTEM, 0, VSC73XX_GLORESET,
678 VSC73XX_GLORESET_PHY_RESET);
679
680 udelay(4);
681
682 return 0;
683 }
684
vsc73xx_init_port(struct vsc73xx * vsc,int port)685 static void vsc73xx_init_port(struct vsc73xx *vsc, int port)
686 {
687 u32 val;
688
689 /* MAC configure, first reset the port and then write defaults */
690 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC,
691 port,
692 VSC73XX_MAC_CFG,
693 VSC73XX_MAC_CFG_RESET);
694
695 /* Take up the port in 1Gbit mode by default, this will be
696 * augmented after auto-negotiation on the PHY-facing
697 * ports.
698 */
699 if (port == CPU_PORT)
700 val = VSC73XX_MAC_CFG_1000M_F_RGMII;
701 else
702 val = VSC73XX_MAC_CFG_1000M_F_PHY;
703
704 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC,
705 port,
706 VSC73XX_MAC_CFG,
707 val |
708 VSC73XX_MAC_CFG_TX_EN |
709 VSC73XX_MAC_CFG_RX_EN);
710
711 /* Flow control for the CPU port:
712 * Use a zero delay pause frame when pause condition is left
713 * Obey pause control frames
714 */
715 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC,
716 port,
717 VSC73XX_FCCONF,
718 VSC73XX_FCCONF_ZERO_PAUSE_EN |
719 VSC73XX_FCCONF_FLOW_CTRL_OBEY);
720
721 /* Issue pause control frames on PHY facing ports.
722 * Allow early initiation of MAC transmission if the amount
723 * of egress data is below 512 bytes on CPU port.
724 * FIXME: enable 20KiB buffers?
725 */
726 if (port == CPU_PORT)
727 val = VSC73XX_Q_MISC_CONF_EARLY_TX_512;
728 else
729 val = VSC73XX_Q_MISC_CONF_MAC_PAUSE_MODE;
730 val |= VSC73XX_Q_MISC_CONF_EXTENT_MEM;
731 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC,
732 port,
733 VSC73XX_Q_MISC_CONF,
734 val);
735
736 /* Flow control MAC: a MAC address used in flow control frames */
737 val = (vsc->addr[5] << 16) | (vsc->addr[4] << 8) | (vsc->addr[3]);
738 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC,
739 port,
740 VSC73XX_FCMACHI,
741 val);
742 val = (vsc->addr[2] << 16) | (vsc->addr[1] << 8) | (vsc->addr[0]);
743 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC,
744 port,
745 VSC73XX_FCMACLO,
746 val);
747
748 /* Tell the categorizer to forward pause frames, not control
749 * frame. Do not drop anything.
750 */
751 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC,
752 port,
753 VSC73XX_CAT_DROP,
754 VSC73XX_CAT_DROP_FWD_PAUSE_ENA);
755
756 /* Clear all counters */
757 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC,
758 port, VSC73XX_C_RX0, 0);
759 }
760
vsc73xx_adjust_enable_port(struct vsc73xx * vsc,int port,struct phy_device * phydev,u32 initval)761 static void vsc73xx_adjust_enable_port(struct vsc73xx *vsc,
762 int port, struct phy_device *phydev,
763 u32 initval)
764 {
765 u32 val = initval;
766 u8 seed;
767
768 /* Reset this port FIXME: break out subroutine */
769 val |= VSC73XX_MAC_CFG_RESET;
770 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, port, VSC73XX_MAC_CFG, val);
771
772 /* Seed the port randomness with randomness */
773 get_random_bytes(&seed, 1);
774 val |= seed << VSC73XX_MAC_CFG_SEED_OFFSET;
775 val |= VSC73XX_MAC_CFG_SEED_LOAD;
776 val |= VSC73XX_MAC_CFG_WEXC_DIS;
777 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, port, VSC73XX_MAC_CFG, val);
778
779 /* Flow control for the PHY facing ports:
780 * Use a zero delay pause frame when pause condition is left
781 * Obey pause control frames
782 * When generating pause frames, use 0xff as pause value
783 */
784 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, port, VSC73XX_FCCONF,
785 VSC73XX_FCCONF_ZERO_PAUSE_EN |
786 VSC73XX_FCCONF_FLOW_CTRL_OBEY |
787 0xff);
788
789 /* Disallow backward dropping of frames from this port */
790 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ARBITER, 0,
791 VSC73XX_SBACKWDROP, BIT(port), 0);
792
793 /* Enable TX, RX, deassert reset, stop loading seed */
794 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_MAC, port,
795 VSC73XX_MAC_CFG,
796 VSC73XX_MAC_CFG_RESET | VSC73XX_MAC_CFG_SEED_LOAD |
797 VSC73XX_MAC_CFG_TX_EN | VSC73XX_MAC_CFG_RX_EN,
798 VSC73XX_MAC_CFG_TX_EN | VSC73XX_MAC_CFG_RX_EN);
799 }
800
vsc73xx_adjust_link(struct dsa_switch * ds,int port,struct phy_device * phydev)801 static void vsc73xx_adjust_link(struct dsa_switch *ds, int port,
802 struct phy_device *phydev)
803 {
804 struct vsc73xx *vsc = ds->priv;
805 u32 val;
806
807 /* Special handling of the CPU-facing port */
808 if (port == CPU_PORT) {
809 /* Other ports are already initialized but not this one */
810 vsc73xx_init_port(vsc, CPU_PORT);
811 /* Select the external port for this interface (EXT_PORT)
812 * Enable the GMII GTX external clock
813 * Use double data rate (DDR mode)
814 */
815 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC,
816 CPU_PORT,
817 VSC73XX_ADVPORTM,
818 VSC73XX_ADVPORTM_EXT_PORT |
819 VSC73XX_ADVPORTM_ENA_GTX |
820 VSC73XX_ADVPORTM_DDR_MODE);
821 }
822
823 /* This is the MAC confiuration that always need to happen
824 * after a PHY or the CPU port comes up or down.
825 */
826 if (!phydev->link) {
827 int ret, err;
828
829 dev_dbg(vsc->dev, "port %d: went down\n",
830 port);
831
832 /* Disable RX on this port */
833 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_MAC, port,
834 VSC73XX_MAC_CFG,
835 VSC73XX_MAC_CFG_RX_EN, 0);
836
837 /* Discard packets */
838 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ARBITER, 0,
839 VSC73XX_ARBDISC, BIT(port), BIT(port));
840
841 /* Wait until queue is empty */
842 ret = read_poll_timeout(vsc73xx_read, err,
843 err < 0 || (val & BIT(port)),
844 VSC73XX_POLL_SLEEP_US,
845 VSC73XX_POLL_TIMEOUT_US, false,
846 vsc, VSC73XX_BLOCK_ARBITER, 0,
847 VSC73XX_ARBEMPTY, &val);
848 if (ret)
849 dev_err(vsc->dev,
850 "timeout waiting for block arbiter\n");
851 else if (err < 0)
852 dev_err(vsc->dev, "error reading arbiter\n");
853
854 /* Put this port into reset */
855 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, port, VSC73XX_MAC_CFG,
856 VSC73XX_MAC_CFG_RESET);
857
858 /* Accept packets again */
859 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ARBITER, 0,
860 VSC73XX_ARBDISC, BIT(port), 0);
861
862 /* Allow backward dropping of frames from this port */
863 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ARBITER, 0,
864 VSC73XX_SBACKWDROP, BIT(port), BIT(port));
865
866 /* Receive mask (disable forwarding) */
867 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0,
868 VSC73XX_RECVMASK, BIT(port), 0);
869
870 return;
871 }
872
873 /* Figure out what speed was negotiated */
874 if (phydev->speed == SPEED_1000) {
875 dev_dbg(vsc->dev, "port %d: 1000 Mbit mode full duplex\n",
876 port);
877
878 /* Set up default for internal port or external RGMII */
879 if (phydev->interface == PHY_INTERFACE_MODE_RGMII)
880 val = VSC73XX_MAC_CFG_1000M_F_RGMII;
881 else
882 val = VSC73XX_MAC_CFG_1000M_F_PHY;
883 vsc73xx_adjust_enable_port(vsc, port, phydev, val);
884 } else if (phydev->speed == SPEED_100) {
885 if (phydev->duplex == DUPLEX_FULL) {
886 val = VSC73XX_MAC_CFG_100_10M_F_PHY;
887 dev_dbg(vsc->dev,
888 "port %d: 100 Mbit full duplex mode\n",
889 port);
890 } else {
891 val = VSC73XX_MAC_CFG_100_10M_H_PHY;
892 dev_dbg(vsc->dev,
893 "port %d: 100 Mbit half duplex mode\n",
894 port);
895 }
896 vsc73xx_adjust_enable_port(vsc, port, phydev, val);
897 } else if (phydev->speed == SPEED_10) {
898 if (phydev->duplex == DUPLEX_FULL) {
899 val = VSC73XX_MAC_CFG_100_10M_F_PHY;
900 dev_dbg(vsc->dev,
901 "port %d: 10 Mbit full duplex mode\n",
902 port);
903 } else {
904 val = VSC73XX_MAC_CFG_100_10M_H_PHY;
905 dev_dbg(vsc->dev,
906 "port %d: 10 Mbit half duplex mode\n",
907 port);
908 }
909 vsc73xx_adjust_enable_port(vsc, port, phydev, val);
910 } else {
911 dev_err(vsc->dev,
912 "could not adjust link: unknown speed\n");
913 }
914
915 /* Enable port (forwarding) in the receieve mask */
916 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_ANALYZER, 0,
917 VSC73XX_RECVMASK, BIT(port), BIT(port));
918 }
919
vsc73xx_port_enable(struct dsa_switch * ds,int port,struct phy_device * phy)920 static int vsc73xx_port_enable(struct dsa_switch *ds, int port,
921 struct phy_device *phy)
922 {
923 struct vsc73xx *vsc = ds->priv;
924
925 dev_info(vsc->dev, "enable port %d\n", port);
926 vsc73xx_init_port(vsc, port);
927
928 return 0;
929 }
930
vsc73xx_port_disable(struct dsa_switch * ds,int port)931 static void vsc73xx_port_disable(struct dsa_switch *ds, int port)
932 {
933 struct vsc73xx *vsc = ds->priv;
934
935 /* Just put the port into reset */
936 vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, port,
937 VSC73XX_MAC_CFG, VSC73XX_MAC_CFG_RESET);
938 }
939
940 static const struct vsc73xx_counter *
vsc73xx_find_counter(struct vsc73xx * vsc,u8 counter,bool tx)941 vsc73xx_find_counter(struct vsc73xx *vsc,
942 u8 counter,
943 bool tx)
944 {
945 const struct vsc73xx_counter *cnts;
946 int num_cnts;
947 int i;
948
949 if (tx) {
950 cnts = vsc73xx_tx_counters;
951 num_cnts = ARRAY_SIZE(vsc73xx_tx_counters);
952 } else {
953 cnts = vsc73xx_rx_counters;
954 num_cnts = ARRAY_SIZE(vsc73xx_rx_counters);
955 }
956
957 for (i = 0; i < num_cnts; i++) {
958 const struct vsc73xx_counter *cnt;
959
960 cnt = &cnts[i];
961 if (cnt->counter == counter)
962 return cnt;
963 }
964
965 return NULL;
966 }
967
vsc73xx_get_strings(struct dsa_switch * ds,int port,u32 stringset,uint8_t * data)968 static void vsc73xx_get_strings(struct dsa_switch *ds, int port, u32 stringset,
969 uint8_t *data)
970 {
971 const struct vsc73xx_counter *cnt;
972 struct vsc73xx *vsc = ds->priv;
973 u8 indices[6];
974 int i, j;
975 u32 val;
976 int ret;
977
978 if (stringset != ETH_SS_STATS)
979 return;
980
981 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_MAC, port,
982 VSC73XX_C_CFG, &val);
983 if (ret)
984 return;
985
986 indices[0] = (val & 0x1f); /* RX counter 0 */
987 indices[1] = ((val >> 5) & 0x1f); /* RX counter 1 */
988 indices[2] = ((val >> 10) & 0x1f); /* RX counter 2 */
989 indices[3] = ((val >> 16) & 0x1f); /* TX counter 0 */
990 indices[4] = ((val >> 21) & 0x1f); /* TX counter 1 */
991 indices[5] = ((val >> 26) & 0x1f); /* TX counter 2 */
992
993 /* The first counters is the RX octets */
994 j = 0;
995 strncpy(data + j * ETH_GSTRING_LEN,
996 "RxEtherStatsOctets", ETH_GSTRING_LEN);
997 j++;
998
999 /* Each port supports recording 3 RX counters and 3 TX counters,
1000 * figure out what counters we use in this set-up and return the
1001 * names of them. The hardware default counters will be number of
1002 * packets on RX/TX, combined broadcast+multicast packets RX/TX and
1003 * total error packets RX/TX.
1004 */
1005 for (i = 0; i < 3; i++) {
1006 cnt = vsc73xx_find_counter(vsc, indices[i], false);
1007 if (cnt)
1008 strncpy(data + j * ETH_GSTRING_LEN,
1009 cnt->name, ETH_GSTRING_LEN);
1010 j++;
1011 }
1012
1013 /* TX stats begins with the number of TX octets */
1014 strncpy(data + j * ETH_GSTRING_LEN,
1015 "TxEtherStatsOctets", ETH_GSTRING_LEN);
1016 j++;
1017
1018 for (i = 3; i < 6; i++) {
1019 cnt = vsc73xx_find_counter(vsc, indices[i], true);
1020 if (cnt)
1021 strncpy(data + j * ETH_GSTRING_LEN,
1022 cnt->name, ETH_GSTRING_LEN);
1023 j++;
1024 }
1025 }
1026
vsc73xx_get_sset_count(struct dsa_switch * ds,int port,int sset)1027 static int vsc73xx_get_sset_count(struct dsa_switch *ds, int port, int sset)
1028 {
1029 /* We only support SS_STATS */
1030 if (sset != ETH_SS_STATS)
1031 return 0;
1032 /* RX and TX packets, then 3 RX counters, 3 TX counters */
1033 return 8;
1034 }
1035
vsc73xx_get_ethtool_stats(struct dsa_switch * ds,int port,uint64_t * data)1036 static void vsc73xx_get_ethtool_stats(struct dsa_switch *ds, int port,
1037 uint64_t *data)
1038 {
1039 struct vsc73xx *vsc = ds->priv;
1040 u8 regs[] = {
1041 VSC73XX_RXOCT,
1042 VSC73XX_C_RX0,
1043 VSC73XX_C_RX1,
1044 VSC73XX_C_RX2,
1045 VSC73XX_TXOCT,
1046 VSC73XX_C_TX0,
1047 VSC73XX_C_TX1,
1048 VSC73XX_C_TX2,
1049 };
1050 u32 val;
1051 int ret;
1052 int i;
1053
1054 for (i = 0; i < ARRAY_SIZE(regs); i++) {
1055 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_MAC, port,
1056 regs[i], &val);
1057 if (ret) {
1058 dev_err(vsc->dev, "error reading counter %d\n", i);
1059 return;
1060 }
1061 data[i] = val;
1062 }
1063 }
1064
vsc73xx_change_mtu(struct dsa_switch * ds,int port,int new_mtu)1065 static int vsc73xx_change_mtu(struct dsa_switch *ds, int port, int new_mtu)
1066 {
1067 struct vsc73xx *vsc = ds->priv;
1068
1069 return vsc73xx_write(vsc, VSC73XX_BLOCK_MAC, port,
1070 VSC73XX_MAXLEN, new_mtu + ETH_HLEN + ETH_FCS_LEN);
1071 }
1072
1073 /* According to application not "VSC7398 Jumbo Frames" setting
1074 * up the frame size to 9.6 KB does not affect the performance on standard
1075 * frames. It is clear from the application note that
1076 * "9.6 kilobytes" == 9600 bytes.
1077 */
vsc73xx_get_max_mtu(struct dsa_switch * ds,int port)1078 static int vsc73xx_get_max_mtu(struct dsa_switch *ds, int port)
1079 {
1080 return 9600 - ETH_HLEN - ETH_FCS_LEN;
1081 }
1082
1083 static const struct dsa_switch_ops vsc73xx_ds_ops = {
1084 .get_tag_protocol = vsc73xx_get_tag_protocol,
1085 .setup = vsc73xx_setup,
1086 .phy_read = vsc73xx_phy_read,
1087 .phy_write = vsc73xx_phy_write,
1088 .adjust_link = vsc73xx_adjust_link,
1089 .get_strings = vsc73xx_get_strings,
1090 .get_ethtool_stats = vsc73xx_get_ethtool_stats,
1091 .get_sset_count = vsc73xx_get_sset_count,
1092 .port_enable = vsc73xx_port_enable,
1093 .port_disable = vsc73xx_port_disable,
1094 .port_change_mtu = vsc73xx_change_mtu,
1095 .port_max_mtu = vsc73xx_get_max_mtu,
1096 };
1097
vsc73xx_gpio_get(struct gpio_chip * chip,unsigned int offset)1098 static int vsc73xx_gpio_get(struct gpio_chip *chip, unsigned int offset)
1099 {
1100 struct vsc73xx *vsc = gpiochip_get_data(chip);
1101 u32 val;
1102 int ret;
1103
1104 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_SYSTEM, 0,
1105 VSC73XX_GPIO, &val);
1106 if (ret)
1107 return ret;
1108
1109 return !!(val & BIT(offset));
1110 }
1111
vsc73xx_gpio_set(struct gpio_chip * chip,unsigned int offset,int val)1112 static void vsc73xx_gpio_set(struct gpio_chip *chip, unsigned int offset,
1113 int val)
1114 {
1115 struct vsc73xx *vsc = gpiochip_get_data(chip);
1116 u32 tmp = val ? BIT(offset) : 0;
1117
1118 vsc73xx_update_bits(vsc, VSC73XX_BLOCK_SYSTEM, 0,
1119 VSC73XX_GPIO, BIT(offset), tmp);
1120 }
1121
vsc73xx_gpio_direction_output(struct gpio_chip * chip,unsigned int offset,int val)1122 static int vsc73xx_gpio_direction_output(struct gpio_chip *chip,
1123 unsigned int offset, int val)
1124 {
1125 struct vsc73xx *vsc = gpiochip_get_data(chip);
1126 u32 tmp = val ? BIT(offset) : 0;
1127
1128 return vsc73xx_update_bits(vsc, VSC73XX_BLOCK_SYSTEM, 0,
1129 VSC73XX_GPIO, BIT(offset + 4) | BIT(offset),
1130 BIT(offset + 4) | tmp);
1131 }
1132
vsc73xx_gpio_direction_input(struct gpio_chip * chip,unsigned int offset)1133 static int vsc73xx_gpio_direction_input(struct gpio_chip *chip,
1134 unsigned int offset)
1135 {
1136 struct vsc73xx *vsc = gpiochip_get_data(chip);
1137
1138 return vsc73xx_update_bits(vsc, VSC73XX_BLOCK_SYSTEM, 0,
1139 VSC73XX_GPIO, BIT(offset + 4),
1140 0);
1141 }
1142
vsc73xx_gpio_get_direction(struct gpio_chip * chip,unsigned int offset)1143 static int vsc73xx_gpio_get_direction(struct gpio_chip *chip,
1144 unsigned int offset)
1145 {
1146 struct vsc73xx *vsc = gpiochip_get_data(chip);
1147 u32 val;
1148 int ret;
1149
1150 ret = vsc73xx_read(vsc, VSC73XX_BLOCK_SYSTEM, 0,
1151 VSC73XX_GPIO, &val);
1152 if (ret)
1153 return ret;
1154
1155 return !(val & BIT(offset + 4));
1156 }
1157
vsc73xx_gpio_probe(struct vsc73xx * vsc)1158 static int vsc73xx_gpio_probe(struct vsc73xx *vsc)
1159 {
1160 int ret;
1161
1162 vsc->gc.label = devm_kasprintf(vsc->dev, GFP_KERNEL, "VSC%04x",
1163 vsc->chipid);
1164 if (!vsc->gc.label)
1165 return -ENOMEM;
1166 vsc->gc.ngpio = 4;
1167 vsc->gc.owner = THIS_MODULE;
1168 vsc->gc.parent = vsc->dev;
1169 vsc->gc.base = -1;
1170 vsc->gc.get = vsc73xx_gpio_get;
1171 vsc->gc.set = vsc73xx_gpio_set;
1172 vsc->gc.direction_input = vsc73xx_gpio_direction_input;
1173 vsc->gc.direction_output = vsc73xx_gpio_direction_output;
1174 vsc->gc.get_direction = vsc73xx_gpio_get_direction;
1175 vsc->gc.can_sleep = true;
1176 ret = devm_gpiochip_add_data(vsc->dev, &vsc->gc, vsc);
1177 if (ret) {
1178 dev_err(vsc->dev, "unable to register GPIO chip\n");
1179 return ret;
1180 }
1181 return 0;
1182 }
1183
vsc73xx_probe(struct vsc73xx * vsc)1184 int vsc73xx_probe(struct vsc73xx *vsc)
1185 {
1186 struct device *dev = vsc->dev;
1187 int ret;
1188
1189 /* Release reset, if any */
1190 vsc->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
1191 if (IS_ERR(vsc->reset)) {
1192 dev_err(dev, "failed to get RESET GPIO\n");
1193 return PTR_ERR(vsc->reset);
1194 }
1195 if (vsc->reset)
1196 /* Wait 20ms according to datasheet table 245 */
1197 msleep(20);
1198
1199 ret = vsc73xx_detect(vsc);
1200 if (ret == -EAGAIN) {
1201 dev_err(vsc->dev,
1202 "Chip seems to be out of control. Assert reset and try again.\n");
1203 gpiod_set_value_cansleep(vsc->reset, 1);
1204 /* Reset pulse should be 20ns minimum, according to datasheet
1205 * table 245, so 10us should be fine
1206 */
1207 usleep_range(10, 100);
1208 gpiod_set_value_cansleep(vsc->reset, 0);
1209 /* Wait 20ms according to datasheet table 245 */
1210 msleep(20);
1211 ret = vsc73xx_detect(vsc);
1212 }
1213 if (ret) {
1214 dev_err(dev, "no chip found (%d)\n", ret);
1215 return -ENODEV;
1216 }
1217
1218 eth_random_addr(vsc->addr);
1219 dev_info(vsc->dev,
1220 "MAC for control frames: %02X:%02X:%02X:%02X:%02X:%02X\n",
1221 vsc->addr[0], vsc->addr[1], vsc->addr[2],
1222 vsc->addr[3], vsc->addr[4], vsc->addr[5]);
1223
1224 /* The VSC7395 switch chips have 5+1 ports which means 5
1225 * ordinary ports and a sixth CPU port facing the processor
1226 * with an RGMII interface. These ports are numbered 0..4
1227 * and 6, so they leave a "hole" in the port map for port 5,
1228 * which is invalid.
1229 *
1230 * The VSC7398 has 8 ports, port 7 is again the CPU port.
1231 *
1232 * We allocate 8 ports and avoid access to the nonexistant
1233 * ports.
1234 */
1235 vsc->ds = devm_kzalloc(dev, sizeof(*vsc->ds), GFP_KERNEL);
1236 if (!vsc->ds)
1237 return -ENOMEM;
1238
1239 vsc->ds->dev = dev;
1240 vsc->ds->num_ports = 8;
1241 vsc->ds->priv = vsc;
1242
1243 vsc->ds->ops = &vsc73xx_ds_ops;
1244 ret = dsa_register_switch(vsc->ds);
1245 if (ret) {
1246 dev_err(dev, "unable to register switch (%d)\n", ret);
1247 return ret;
1248 }
1249
1250 ret = vsc73xx_gpio_probe(vsc);
1251 if (ret) {
1252 dsa_unregister_switch(vsc->ds);
1253 return ret;
1254 }
1255
1256 return 0;
1257 }
1258 EXPORT_SYMBOL(vsc73xx_probe);
1259
vsc73xx_remove(struct vsc73xx * vsc)1260 void vsc73xx_remove(struct vsc73xx *vsc)
1261 {
1262 dsa_unregister_switch(vsc->ds);
1263 gpiod_set_value(vsc->reset, 1);
1264 }
1265 EXPORT_SYMBOL(vsc73xx_remove);
1266
vsc73xx_shutdown(struct vsc73xx * vsc)1267 void vsc73xx_shutdown(struct vsc73xx *vsc)
1268 {
1269 dsa_switch_shutdown(vsc->ds);
1270 }
1271 EXPORT_SYMBOL(vsc73xx_shutdown);
1272
1273 MODULE_AUTHOR("Linus Walleij <linus.walleij@linaro.org>");
1274 MODULE_DESCRIPTION("Vitesse VSC7385/7388/7395/7398 driver");
1275 MODULE_LICENSE("GPL v2");
1276