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Searched refs:VPU_40XX_TOP_NOC_QREQN (Results 1 – 2 of 2) sorted by relevance

/openbmc/linux/drivers/accel/ivpu/
H A Divpu_hw_40xx.c334 u32 val = REGV_RD32(VPU_40XX_TOP_NOC_QREQN); in ivpu_boot_top_noc_qrenqn_check()
336 if (!REG_TEST_FLD_NUM(VPU_40XX_TOP_NOC_QREQN, CPU_CTRL, exp_val, val) || in ivpu_boot_top_noc_qrenqn_check()
337 !REG_TEST_FLD_NUM(VPU_40XX_TOP_NOC_QREQN, HOSTIF_L2CACHE, exp_val, val)) in ivpu_boot_top_noc_qrenqn_check()
442 val = REGV_RD32(VPU_40XX_TOP_NOC_QREQN); in ivpu_boot_host_ss_top_noc_drive()
444 val = REG_SET_FLD(VPU_40XX_TOP_NOC_QREQN, CPU_CTRL, val); in ivpu_boot_host_ss_top_noc_drive()
445 val = REG_SET_FLD(VPU_40XX_TOP_NOC_QREQN, HOSTIF_L2CACHE, val); in ivpu_boot_host_ss_top_noc_drive()
447 val = REG_CLR_FLD(VPU_40XX_TOP_NOC_QREQN, CPU_CTRL, val); in ivpu_boot_host_ss_top_noc_drive()
448 val = REG_CLR_FLD(VPU_40XX_TOP_NOC_QREQN, HOSTIF_L2CACHE, val); in ivpu_boot_host_ss_top_noc_drive()
450 REGV_WR32(VPU_40XX_TOP_NOC_QREQN, val); in ivpu_boot_host_ss_top_noc_drive()
H A Divpu_hw_40xx_reg.h140 #define VPU_40XX_TOP_NOC_QREQN 0x00000160u macro