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Searched refs:VPU_40XX_HOST_SS_ICB_STATUS_0 (Results 1 – 2 of 2) sorted by relevance

/openbmc/linux/drivers/accel/ivpu/
H A Divpu_hw_40xx.c47 (REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_0_INT)) | \
48 (REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_1_INT)) | \
49 (REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_2_INT)) | \
50 (REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, NOC_FIREWALL_INT)) | \
51 (REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_0_INT)) | \
52 (REG_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, CPU_INT_REDIRECT_1_INT)))
1020 u32 status = REGV_RD32(VPU_40XX_HOST_SS_ICB_STATUS_0) & ICB_0_IRQ_MASK; in ivpu_hw_40xx_irqv_handler()
1028 if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_0_INT, status)) in ivpu_hw_40xx_irqv_handler()
1034 if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_1_INT, status)) in ivpu_hw_40xx_irqv_handler()
1037 if (REG_TEST_FLD(VPU_40XX_HOST_SS_ICB_STATUS_0, MMU_IRQ_2_INT, status)) in ivpu_hw_40xx_irqv_handler()
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H A Divpu_hw_40xx_reg.h161 #define VPU_40XX_HOST_SS_ICB_STATUS_0 0x00010210u macro