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Searched refs:VPLL (Results 1 – 7 of 7) sorted by relevance

/openbmc/u-boot/arch/arm/mach-s5pc1xx/include/mach/
H A Dclk.h15 #define VPLL 4 macro
/openbmc/u-boot/arch/arm/mach-exynos/
H A Dclock.c144 } else if (pllreg == VPLL) { in exynos_get_pll_clk()
202 case VPLL: in exynos4_get_pll_clk()
232 case VPLL: in exynos4x12_get_pll_clk()
263 case VPLL: in exynos5_get_pll_clk()
321 case VPLL: in exynos542x_get_pll_clk()
443 sclk = exynos5_get_pll_clk(VPLL); in exynos5_get_periph_rate()
656 sclk = get_pll_clk(VPLL); in exynos4_get_pwm_clk()
717 sclk = get_pll_clk(VPLL); in exynos4_get_uart_clk()
763 sclk = get_pll_clk(VPLL); in exynos4x12_get_uart_clk()
799 sclk = get_pll_clk(VPLL); in exynos4_get_mmc_clk()
[all …]
/openbmc/u-boot/arch/mips/mach-jz47xx/jz4780/
H A Dpll.c358 VPLL, enumerator
456 { CPM_LPCDR, VPLL, 30 }, in pll_init()
457 { CPM_LPCDR1, VPLL, 30 }, in pll_init()
459 { CPM_HDMICDR, VPLL, 30 }, in pll_init()
474 pll_init_one(VPLL, JZ4780_VPLL_M, JZ4780_VPLL_N, JZ4780_VPLL_OD); in pll_init()
/openbmc/u-boot/arch/arm/mach-exynos/include/mach/
H A Dclk.h14 #define VPLL 4 macro
/openbmc/u-boot/arch/arm/mach-s5pc1xx/
H A Dclock.c93 case VPLL: in s5pc110_get_pll_clk()
/openbmc/u-boot/doc/device-tree-bindings/video/
H A Dexynos-fb.txt55 samsung,pclk-name: parent clock identifier: 1(MPLL), 2(EPLL), 3(VPLL)
/openbmc/u-boot/board/samsung/goni/
H A Dlowlevel_init.S333 ldr r1, =0x10001111 @ A, M, E, VPLL Muxing