| /openbmc/u-boot/arch/arm/mach-exynos/ |
| H A D | clock.c | 144 } else if (pllreg == VPLL) { in exynos_get_pll_clk()
202 case VPLL: in exynos4_get_pll_clk()
232 case VPLL: in exynos4x12_get_pll_clk()
263 case VPLL: in exynos5_get_pll_clk()
321 case VPLL: in exynos542x_get_pll_clk()
656 sclk = get_pll_clk(VPLL); in exynos4_get_pwm_clk()
717 sclk = get_pll_clk(VPLL); in exynos4_get_uart_clk()
763 sclk = get_pll_clk(VPLL); in exynos4x12_get_uart_clk()
799 sclk = get_pll_clk(VPLL); in exynos4_get_mmc_clk()
937 sclk = get_pll_clk(VPLL); in exynos4_get_lcd_clk()
[all …]
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| /openbmc/u-boot/arch/mips/mach-jz47xx/jz4780/ |
| H A D | pll.c | 358 VPLL, enumerator
456 { CPM_LPCDR, VPLL, 30 }, in pll_init()
457 { CPM_LPCDR1, VPLL, 30 }, in pll_init()
459 { CPM_HDMICDR, VPLL, 30 }, in pll_init()
474 pll_init_one(VPLL, JZ4780_VPLL_M, JZ4780_VPLL_N, JZ4780_VPLL_OD); in pll_init()
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| /openbmc/u-boot/arch/arm/mach-s5pc1xx/include/mach/ |
| H A D | clk.h | 15 #define VPLL 4 macro
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| /openbmc/u-boot/arch/arm/mach-exynos/include/mach/ |
| H A D | clk.h | 14 #define VPLL 4 macro
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| /openbmc/linux/arch/arm64/boot/dts/nuvoton/ |
| H A D | ma35d1-iot-512m.dts | 45 <&clk VPLL>;
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| H A D | ma35d1-som-256m.dts | 45 <&clk VPLL>;
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| /openbmc/linux/include/dt-bindings/clock/ |
| H A D | xlnx-zynqmp-clk.h | 16 #define VPLL 4 macro
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| H A D | nuvoton,ma35d1-clk.h | 24 #define VPLL 13 macro
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| /openbmc/linux/Documentation/devicetree/bindings/clock/ |
| H A D | nuvoton,ma35d1-clk.yaml | 37 EPLL, and VPLL in sequential.
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| /openbmc/linux/drivers/clk/nuvoton/ |
| H A D | clk-ma35d1-pll.c | 238 case VPLL: in ma35d1_clk_pll_recalc_rate()
270 case VPLL: in ma35d1_clk_pll_round_rate()
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| H A D | clk-ma35d1.c | 510 hws[VPLL] = ma35d1_reg_clk_pll(dev, VPLL, pllmode[4], "vpll", in ma35d1_clocks_probe()
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| /openbmc/linux/drivers/regulator/ |
| H A D | cpcap-regulator.c | 369 CPCAP_REG(VPLL, CPCAP_REG_VPLLC, CPCAP_REG_ASSIGN3,
445 CPCAP_REG(VPLL, CPCAP_REG_VPLLC, CPCAP_REG_ASSIGN3,
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| H A D | mc13892-regulator.c | 273 MC13892_DEFINE_REGU(VPLL, vpll, REGULATORMODE0, REGULATORSETTING0,
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| H A D | tps65910-regulator.c | 283 EXT_CONTROL_REG_BITS(VPLL, 0, 6),
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| /openbmc/u-boot/arch/arm/mach-s5pc1xx/ |
| H A D | clock.c | 93 case VPLL: in s5pc110_get_pll_clk()
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| /openbmc/linux/arch/arm/boot/dts/nxp/imx/ |
| H A D | imx53-qsrb.dts | 96 regulator-name = "VPLL";
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| /openbmc/u-boot/doc/device-tree-bindings/video/ |
| H A D | exynos-fb.txt | 55 samsung,pclk-name: parent clock identifier: 1(MPLL), 2(EPLL), 3(VPLL)
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| /openbmc/linux/Documentation/devicetree/bindings/mfd/ |
| H A D | mc13xxx.txt | 95 vpll : regulator VPLL (register 32, bit 15)
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| H A D | tps65910.txt | 39 vcc5-supply: VPLL and VDAC input.
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| /openbmc/linux/arch/arm/boot/dts/ti/omap/ |
| H A D | motorola-cpcap-mapphone.dtsi | 205 vpll: VPLL {
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| H A D | omap3-n900.dts | 452 regulator-name = "VPLL";
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| /openbmc/u-boot/board/samsung/goni/ |
| H A D | lowlevel_init.S | 333 ldr r1, =0x10001111 @ A, M, E, VPLL Muxing
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| /openbmc/linux/drivers/clk/ingenic/ |
| H A D | jz4780-cgu.c | 313 .pll = DEF_PLL(VPLL),
|