1 // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2 /*
3 * Copyright (c) 2020 Rockchip Electronics Co., Ltd.
4 * Author: Andy Yan <andy.yan@rock-chips.com>
5 */
6 #include <linux/bitfield.h>
7 #include <linux/clk.h>
8 #include <linux/component.h>
9 #include <linux/delay.h>
10 #include <linux/iopoll.h>
11 #include <linux/kernel.h>
12 #include <linux/media-bus-format.h>
13 #include <linux/mfd/syscon.h>
14 #include <linux/module.h>
15 #include <linux/of.h>
16 #include <linux/of_graph.h>
17 #include <linux/platform_device.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/regmap.h>
20 #include <linux/swab.h>
21
22 #include <drm/drm.h>
23 #include <drm/drm_atomic.h>
24 #include <drm/drm_atomic_uapi.h>
25 #include <drm/drm_blend.h>
26 #include <drm/drm_crtc.h>
27 #include <drm/drm_debugfs.h>
28 #include <drm/drm_flip_work.h>
29 #include <drm/drm_framebuffer.h>
30 #include <drm/drm_probe_helper.h>
31 #include <drm/drm_vblank.h>
32
33 #include <uapi/linux/videodev2.h>
34 #include <dt-bindings/soc/rockchip,vop2.h>
35
36 #include "rockchip_drm_gem.h"
37 #include "rockchip_drm_fb.h"
38 #include "rockchip_drm_vop2.h"
39 #include "rockchip_rgb.h"
40
41 /*
42 * VOP2 architecture
43 *
44 +----------+ +-------------+ +-----------+
45 | Cluster | | Sel 1 from 6| | 1 from 3 |
46 | window0 | | Layer0 | | RGB |
47 +----------+ +-------------+ +---------------+ +-------------+ +-----------+
48 +----------+ +-------------+ |N from 6 layers| | |
49 | Cluster | | Sel 1 from 6| | Overlay0 +--->| Video Port0 | +-----------+
50 | window1 | | Layer1 | | | | | | 1 from 3 |
51 +----------+ +-------------+ +---------------+ +-------------+ | LVDS |
52 +----------+ +-------------+ +-----------+
53 | Esmart | | Sel 1 from 6|
54 | window0 | | Layer2 | +---------------+ +-------------+ +-----------+
55 +----------+ +-------------+ |N from 6 Layers| | | +--> | 1 from 3 |
56 +----------+ +-------------+ --------> | Overlay1 +--->| Video Port1 | | MIPI |
57 | Esmart | | Sel 1 from 6| --------> | | | | +-----------+
58 | Window1 | | Layer3 | +---------------+ +-------------+
59 +----------+ +-------------+ +-----------+
60 +----------+ +-------------+ | 1 from 3 |
61 | Smart | | Sel 1 from 6| +---------------+ +-------------+ | HDMI |
62 | Window0 | | Layer4 | |N from 6 Layers| | | +-----------+
63 +----------+ +-------------+ | Overlay2 +--->| Video Port2 |
64 +----------+ +-------------+ | | | | +-----------+
65 | Smart | | Sel 1 from 6| +---------------+ +-------------+ | 1 from 3 |
66 | Window1 | | Layer5 | | eDP |
67 +----------+ +-------------+ +-----------+
68 *
69 */
70
71 enum vop2_data_format {
72 VOP2_FMT_ARGB8888 = 0,
73 VOP2_FMT_RGB888,
74 VOP2_FMT_RGB565,
75 VOP2_FMT_XRGB101010,
76 VOP2_FMT_YUV420SP,
77 VOP2_FMT_YUV422SP,
78 VOP2_FMT_YUV444SP,
79 VOP2_FMT_YUYV422 = 8,
80 VOP2_FMT_YUYV420,
81 VOP2_FMT_VYUY422,
82 VOP2_FMT_VYUY420,
83 VOP2_FMT_YUV420SP_TILE_8x4 = 0x10,
84 VOP2_FMT_YUV420SP_TILE_16x2,
85 VOP2_FMT_YUV422SP_TILE_8x4,
86 VOP2_FMT_YUV422SP_TILE_16x2,
87 VOP2_FMT_YUV420SP_10,
88 VOP2_FMT_YUV422SP_10,
89 VOP2_FMT_YUV444SP_10,
90 };
91
92 enum vop2_afbc_format {
93 VOP2_AFBC_FMT_RGB565,
94 VOP2_AFBC_FMT_ARGB2101010 = 2,
95 VOP2_AFBC_FMT_YUV420_10BIT,
96 VOP2_AFBC_FMT_RGB888,
97 VOP2_AFBC_FMT_ARGB8888,
98 VOP2_AFBC_FMT_YUV420 = 9,
99 VOP2_AFBC_FMT_YUV422 = 0xb,
100 VOP2_AFBC_FMT_YUV422_10BIT = 0xe,
101 VOP2_AFBC_FMT_INVALID = -1,
102 };
103
104 union vop2_alpha_ctrl {
105 u32 val;
106 struct {
107 /* [0:1] */
108 u32 color_mode:1;
109 u32 alpha_mode:1;
110 /* [2:3] */
111 u32 blend_mode:2;
112 u32 alpha_cal_mode:1;
113 /* [5:7] */
114 u32 factor_mode:3;
115 /* [8:9] */
116 u32 alpha_en:1;
117 u32 src_dst_swap:1;
118 u32 reserved:6;
119 /* [16:23] */
120 u32 glb_alpha:8;
121 } bits;
122 };
123
124 struct vop2_alpha {
125 union vop2_alpha_ctrl src_color_ctrl;
126 union vop2_alpha_ctrl dst_color_ctrl;
127 union vop2_alpha_ctrl src_alpha_ctrl;
128 union vop2_alpha_ctrl dst_alpha_ctrl;
129 };
130
131 struct vop2_alpha_config {
132 bool src_premulti_en;
133 bool dst_premulti_en;
134 bool src_pixel_alpha_en;
135 bool dst_pixel_alpha_en;
136 u16 src_glb_alpha_value;
137 u16 dst_glb_alpha_value;
138 };
139
140 struct vop2_win {
141 struct vop2 *vop2;
142 struct drm_plane base;
143 const struct vop2_win_data *data;
144 struct regmap_field *reg[VOP2_WIN_MAX_REG];
145
146 /**
147 * @win_id: graphic window id, a cluster may be split into two
148 * graphics windows.
149 */
150 u8 win_id;
151 u8 delay;
152 u32 offset;
153
154 enum drm_plane_type type;
155 };
156
157 struct vop2_video_port {
158 struct drm_crtc crtc;
159 struct vop2 *vop2;
160 struct clk *dclk;
161 unsigned int id;
162 const struct vop2_video_port_regs *regs;
163 const struct vop2_video_port_data *data;
164
165 struct completion dsp_hold_completion;
166
167 /**
168 * @win_mask: Bitmask of windows attached to the video port;
169 */
170 u32 win_mask;
171
172 struct vop2_win *primary_plane;
173 struct drm_pending_vblank_event *event;
174
175 unsigned int nlayers;
176 };
177
178 struct vop2 {
179 struct device *dev;
180 struct drm_device *drm;
181 struct vop2_video_port vps[ROCKCHIP_MAX_CRTC];
182
183 const struct vop2_data *data;
184 /*
185 * Number of windows that are registered as plane, may be less than the
186 * total number of hardware windows.
187 */
188 u32 registered_num_wins;
189
190 void __iomem *regs;
191 struct regmap *map;
192
193 struct regmap *grf;
194
195 /* physical map length of vop2 register */
196 u32 len;
197
198 void __iomem *lut_regs;
199
200 /* protects crtc enable/disable */
201 struct mutex vop2_lock;
202
203 int irq;
204
205 /*
206 * Some global resources are shared between all video ports(crtcs), so
207 * we need a ref counter here.
208 */
209 unsigned int enable_count;
210 struct clk *hclk;
211 struct clk *aclk;
212
213 /* optional internal rgb encoder */
214 struct rockchip_rgb *rgb;
215
216 /* must be put at the end of the struct */
217 struct vop2_win win[];
218 };
219
to_vop2_video_port(struct drm_crtc * crtc)220 static struct vop2_video_port *to_vop2_video_port(struct drm_crtc *crtc)
221 {
222 return container_of(crtc, struct vop2_video_port, crtc);
223 }
224
to_vop2_win(struct drm_plane * p)225 static struct vop2_win *to_vop2_win(struct drm_plane *p)
226 {
227 return container_of(p, struct vop2_win, base);
228 }
229
vop2_lock(struct vop2 * vop2)230 static void vop2_lock(struct vop2 *vop2)
231 {
232 mutex_lock(&vop2->vop2_lock);
233 }
234
vop2_unlock(struct vop2 * vop2)235 static void vop2_unlock(struct vop2 *vop2)
236 {
237 mutex_unlock(&vop2->vop2_lock);
238 }
239
vop2_writel(struct vop2 * vop2,u32 offset,u32 v)240 static void vop2_writel(struct vop2 *vop2, u32 offset, u32 v)
241 {
242 regmap_write(vop2->map, offset, v);
243 }
244
vop2_vp_write(struct vop2_video_port * vp,u32 offset,u32 v)245 static void vop2_vp_write(struct vop2_video_port *vp, u32 offset, u32 v)
246 {
247 regmap_write(vp->vop2->map, vp->data->offset + offset, v);
248 }
249
vop2_readl(struct vop2 * vop2,u32 offset)250 static u32 vop2_readl(struct vop2 *vop2, u32 offset)
251 {
252 u32 val;
253
254 regmap_read(vop2->map, offset, &val);
255
256 return val;
257 }
258
vop2_win_write(const struct vop2_win * win,unsigned int reg,u32 v)259 static void vop2_win_write(const struct vop2_win *win, unsigned int reg, u32 v)
260 {
261 regmap_field_write(win->reg[reg], v);
262 }
263
vop2_cluster_window(const struct vop2_win * win)264 static bool vop2_cluster_window(const struct vop2_win *win)
265 {
266 return win->data->feature & WIN_FEATURE_CLUSTER;
267 }
268
vop2_cfg_done(struct vop2_video_port * vp)269 static void vop2_cfg_done(struct vop2_video_port *vp)
270 {
271 struct vop2 *vop2 = vp->vop2;
272
273 regmap_set_bits(vop2->map, RK3568_REG_CFG_DONE,
274 BIT(vp->id) | RK3568_REG_CFG_DONE__GLB_CFG_DONE_EN);
275 }
276
vop2_win_disable(struct vop2_win * win)277 static void vop2_win_disable(struct vop2_win *win)
278 {
279 vop2_win_write(win, VOP2_WIN_ENABLE, 0);
280
281 if (vop2_cluster_window(win))
282 vop2_win_write(win, VOP2_WIN_CLUSTER_ENABLE, 0);
283 }
284
vop2_convert_format(u32 format)285 static enum vop2_data_format vop2_convert_format(u32 format)
286 {
287 switch (format) {
288 case DRM_FORMAT_XRGB8888:
289 case DRM_FORMAT_ARGB8888:
290 case DRM_FORMAT_XBGR8888:
291 case DRM_FORMAT_ABGR8888:
292 return VOP2_FMT_ARGB8888;
293 case DRM_FORMAT_RGB888:
294 case DRM_FORMAT_BGR888:
295 return VOP2_FMT_RGB888;
296 case DRM_FORMAT_RGB565:
297 case DRM_FORMAT_BGR565:
298 return VOP2_FMT_RGB565;
299 case DRM_FORMAT_NV12:
300 return VOP2_FMT_YUV420SP;
301 case DRM_FORMAT_NV16:
302 return VOP2_FMT_YUV422SP;
303 case DRM_FORMAT_NV24:
304 return VOP2_FMT_YUV444SP;
305 case DRM_FORMAT_YUYV:
306 case DRM_FORMAT_YVYU:
307 return VOP2_FMT_VYUY422;
308 case DRM_FORMAT_VYUY:
309 case DRM_FORMAT_UYVY:
310 return VOP2_FMT_YUYV422;
311 default:
312 DRM_ERROR("unsupported format[%08x]\n", format);
313 return -EINVAL;
314 }
315 }
316
vop2_convert_afbc_format(u32 format)317 static enum vop2_afbc_format vop2_convert_afbc_format(u32 format)
318 {
319 switch (format) {
320 case DRM_FORMAT_XRGB8888:
321 case DRM_FORMAT_ARGB8888:
322 case DRM_FORMAT_XBGR8888:
323 case DRM_FORMAT_ABGR8888:
324 return VOP2_AFBC_FMT_ARGB8888;
325 case DRM_FORMAT_RGB888:
326 case DRM_FORMAT_BGR888:
327 return VOP2_AFBC_FMT_RGB888;
328 case DRM_FORMAT_RGB565:
329 case DRM_FORMAT_BGR565:
330 return VOP2_AFBC_FMT_RGB565;
331 case DRM_FORMAT_NV12:
332 return VOP2_AFBC_FMT_YUV420;
333 case DRM_FORMAT_NV16:
334 return VOP2_AFBC_FMT_YUV422;
335 default:
336 return VOP2_AFBC_FMT_INVALID;
337 }
338
339 return VOP2_AFBC_FMT_INVALID;
340 }
341
vop2_win_rb_swap(u32 format)342 static bool vop2_win_rb_swap(u32 format)
343 {
344 switch (format) {
345 case DRM_FORMAT_XBGR8888:
346 case DRM_FORMAT_ABGR8888:
347 case DRM_FORMAT_BGR888:
348 case DRM_FORMAT_BGR565:
349 return true;
350 default:
351 return false;
352 }
353 }
354
vop2_afbc_rb_swap(u32 format)355 static bool vop2_afbc_rb_swap(u32 format)
356 {
357 switch (format) {
358 case DRM_FORMAT_NV24:
359 return true;
360 default:
361 return false;
362 }
363 }
364
vop2_afbc_uv_swap(u32 format)365 static bool vop2_afbc_uv_swap(u32 format)
366 {
367 switch (format) {
368 case DRM_FORMAT_NV12:
369 case DRM_FORMAT_NV16:
370 return true;
371 default:
372 return false;
373 }
374 }
375
vop2_win_uv_swap(u32 format)376 static bool vop2_win_uv_swap(u32 format)
377 {
378 switch (format) {
379 case DRM_FORMAT_NV12:
380 case DRM_FORMAT_NV16:
381 case DRM_FORMAT_NV24:
382 return true;
383 default:
384 return false;
385 }
386 }
387
vop2_win_dither_up(u32 format)388 static bool vop2_win_dither_up(u32 format)
389 {
390 switch (format) {
391 case DRM_FORMAT_BGR565:
392 case DRM_FORMAT_RGB565:
393 return true;
394 default:
395 return false;
396 }
397 }
398
vop2_output_uv_swap(u32 bus_format,u32 output_mode)399 static bool vop2_output_uv_swap(u32 bus_format, u32 output_mode)
400 {
401 /*
402 * FIXME:
403 *
404 * There is no media type for YUV444 output,
405 * so when out_mode is AAAA or P888, assume output is YUV444 on
406 * yuv format.
407 *
408 * From H/W testing, YUV444 mode need a rb swap.
409 */
410 if (bus_format == MEDIA_BUS_FMT_YVYU8_1X16 ||
411 bus_format == MEDIA_BUS_FMT_VYUY8_1X16 ||
412 bus_format == MEDIA_BUS_FMT_YVYU8_2X8 ||
413 bus_format == MEDIA_BUS_FMT_VYUY8_2X8 ||
414 ((bus_format == MEDIA_BUS_FMT_YUV8_1X24 ||
415 bus_format == MEDIA_BUS_FMT_YUV10_1X30) &&
416 (output_mode == ROCKCHIP_OUT_MODE_AAAA ||
417 output_mode == ROCKCHIP_OUT_MODE_P888)))
418 return true;
419 else
420 return false;
421 }
422
is_yuv_output(u32 bus_format)423 static bool is_yuv_output(u32 bus_format)
424 {
425 switch (bus_format) {
426 case MEDIA_BUS_FMT_YUV8_1X24:
427 case MEDIA_BUS_FMT_YUV10_1X30:
428 case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
429 case MEDIA_BUS_FMT_UYYVYY10_0_5X30:
430 case MEDIA_BUS_FMT_YUYV8_2X8:
431 case MEDIA_BUS_FMT_YVYU8_2X8:
432 case MEDIA_BUS_FMT_UYVY8_2X8:
433 case MEDIA_BUS_FMT_VYUY8_2X8:
434 case MEDIA_BUS_FMT_YUYV8_1X16:
435 case MEDIA_BUS_FMT_YVYU8_1X16:
436 case MEDIA_BUS_FMT_UYVY8_1X16:
437 case MEDIA_BUS_FMT_VYUY8_1X16:
438 return true;
439 default:
440 return false;
441 }
442 }
443
rockchip_afbc(struct drm_plane * plane,u64 modifier)444 static bool rockchip_afbc(struct drm_plane *plane, u64 modifier)
445 {
446 int i;
447
448 if (modifier == DRM_FORMAT_MOD_LINEAR)
449 return false;
450
451 for (i = 0 ; i < plane->modifier_count; i++)
452 if (plane->modifiers[i] == modifier)
453 return true;
454
455 return false;
456 }
457
rockchip_vop2_mod_supported(struct drm_plane * plane,u32 format,u64 modifier)458 static bool rockchip_vop2_mod_supported(struct drm_plane *plane, u32 format,
459 u64 modifier)
460 {
461 struct vop2_win *win = to_vop2_win(plane);
462 struct vop2 *vop2 = win->vop2;
463
464 if (modifier == DRM_FORMAT_MOD_INVALID)
465 return false;
466
467 if (vop2->data->soc_id == 3568 || vop2->data->soc_id == 3566) {
468 if (vop2_cluster_window(win)) {
469 if (modifier == DRM_FORMAT_MOD_LINEAR) {
470 drm_dbg_kms(vop2->drm,
471 "Cluster window only supports format with afbc\n");
472 return false;
473 }
474 }
475 }
476
477 if (modifier == DRM_FORMAT_MOD_LINEAR)
478 return true;
479
480 if (!rockchip_afbc(plane, modifier)) {
481 drm_err(vop2->drm, "Unsupported format modifier 0x%llx\n",
482 modifier);
483
484 return false;
485 }
486
487 return vop2_convert_afbc_format(format) >= 0;
488 }
489
vop2_afbc_transform_offset(struct drm_plane_state * pstate,bool afbc_half_block_en)490 static u32 vop2_afbc_transform_offset(struct drm_plane_state *pstate,
491 bool afbc_half_block_en)
492 {
493 struct drm_rect *src = &pstate->src;
494 struct drm_framebuffer *fb = pstate->fb;
495 u32 bpp = fb->format->cpp[0] * 8;
496 u32 vir_width = (fb->pitches[0] << 3) / bpp;
497 u32 width = drm_rect_width(src) >> 16;
498 u32 height = drm_rect_height(src) >> 16;
499 u32 act_xoffset = src->x1 >> 16;
500 u32 act_yoffset = src->y1 >> 16;
501 u32 align16_crop = 0;
502 u32 align64_crop = 0;
503 u32 height_tmp;
504 u8 tx, ty;
505 u8 bottom_crop_line_num = 0;
506
507 /* 16 pixel align */
508 if (height & 0xf)
509 align16_crop = 16 - (height & 0xf);
510
511 height_tmp = height + align16_crop;
512
513 /* 64 pixel align */
514 if (height_tmp & 0x3f)
515 align64_crop = 64 - (height_tmp & 0x3f);
516
517 bottom_crop_line_num = align16_crop + align64_crop;
518
519 switch (pstate->rotation &
520 (DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y |
521 DRM_MODE_ROTATE_90 | DRM_MODE_ROTATE_270)) {
522 case DRM_MODE_REFLECT_X | DRM_MODE_REFLECT_Y:
523 tx = 16 - ((act_xoffset + width) & 0xf);
524 ty = bottom_crop_line_num - act_yoffset;
525 break;
526 case DRM_MODE_REFLECT_X | DRM_MODE_ROTATE_90:
527 tx = bottom_crop_line_num - act_yoffset;
528 ty = vir_width - width - act_xoffset;
529 break;
530 case DRM_MODE_REFLECT_X | DRM_MODE_ROTATE_270:
531 tx = act_yoffset;
532 ty = act_xoffset;
533 break;
534 case DRM_MODE_REFLECT_X:
535 tx = 16 - ((act_xoffset + width) & 0xf);
536 ty = act_yoffset;
537 break;
538 case DRM_MODE_REFLECT_Y:
539 tx = act_xoffset;
540 ty = bottom_crop_line_num - act_yoffset;
541 break;
542 case DRM_MODE_ROTATE_90:
543 tx = bottom_crop_line_num - act_yoffset;
544 ty = act_xoffset;
545 break;
546 case DRM_MODE_ROTATE_270:
547 tx = act_yoffset;
548 ty = vir_width - width - act_xoffset;
549 break;
550 case 0:
551 tx = act_xoffset;
552 ty = act_yoffset;
553 break;
554 }
555
556 if (afbc_half_block_en)
557 ty &= 0x7f;
558
559 #define TRANSFORM_XOFFSET GENMASK(7, 0)
560 #define TRANSFORM_YOFFSET GENMASK(23, 16)
561 return FIELD_PREP(TRANSFORM_XOFFSET, tx) |
562 FIELD_PREP(TRANSFORM_YOFFSET, ty);
563 }
564
565 /*
566 * A Cluster window has 2048 x 16 line buffer, which can
567 * works at 2048 x 16(Full) or 4096 x 8 (Half) mode.
568 * for Cluster_lb_mode register:
569 * 0: half mode, for plane input width range 2048 ~ 4096
570 * 1: half mode, for cluster work at 2 * 2048 plane mode
571 * 2: half mode, for rotate_90/270 mode
572 *
573 */
vop2_get_cluster_lb_mode(struct vop2_win * win,struct drm_plane_state * pstate)574 static int vop2_get_cluster_lb_mode(struct vop2_win *win,
575 struct drm_plane_state *pstate)
576 {
577 if ((pstate->rotation & DRM_MODE_ROTATE_270) ||
578 (pstate->rotation & DRM_MODE_ROTATE_90))
579 return 2;
580 else
581 return 0;
582 }
583
vop2_scale_factor(u32 src,u32 dst)584 static u16 vop2_scale_factor(u32 src, u32 dst)
585 {
586 u32 fac;
587 int shift;
588
589 if (src == dst)
590 return 0;
591
592 if (dst < 2)
593 return U16_MAX;
594
595 if (src < 2)
596 return 0;
597
598 if (src > dst)
599 shift = 12;
600 else
601 shift = 16;
602
603 src--;
604 dst--;
605
606 fac = DIV_ROUND_UP(src << shift, dst) - 1;
607
608 if (fac > U16_MAX)
609 return U16_MAX;
610
611 return fac;
612 }
613
vop2_setup_scale(struct vop2 * vop2,const struct vop2_win * win,u32 src_w,u32 src_h,u32 dst_w,u32 dst_h,u32 pixel_format)614 static void vop2_setup_scale(struct vop2 *vop2, const struct vop2_win *win,
615 u32 src_w, u32 src_h, u32 dst_w,
616 u32 dst_h, u32 pixel_format)
617 {
618 const struct drm_format_info *info;
619 u16 hor_scl_mode, ver_scl_mode;
620 u16 hscl_filter_mode, vscl_filter_mode;
621 uint16_t cbcr_src_w = src_w;
622 uint16_t cbcr_src_h = src_h;
623 u8 gt2 = 0;
624 u8 gt4 = 0;
625 u32 val;
626
627 info = drm_format_info(pixel_format);
628
629 if (src_h >= (4 * dst_h)) {
630 gt4 = 1;
631 src_h >>= 2;
632 } else if (src_h >= (2 * dst_h)) {
633 gt2 = 1;
634 src_h >>= 1;
635 }
636
637 hor_scl_mode = scl_get_scl_mode(src_w, dst_w);
638 ver_scl_mode = scl_get_scl_mode(src_h, dst_h);
639
640 if (hor_scl_mode == SCALE_UP)
641 hscl_filter_mode = VOP2_SCALE_UP_BIC;
642 else
643 hscl_filter_mode = VOP2_SCALE_DOWN_BIL;
644
645 if (ver_scl_mode == SCALE_UP)
646 vscl_filter_mode = VOP2_SCALE_UP_BIL;
647 else
648 vscl_filter_mode = VOP2_SCALE_DOWN_BIL;
649
650 /*
651 * RK3568 VOP Esmart/Smart dsp_w should be even pixel
652 * at scale down mode
653 */
654 if (!(win->data->feature & WIN_FEATURE_AFBDC)) {
655 if ((hor_scl_mode == SCALE_DOWN) && (dst_w & 0x1)) {
656 drm_dbg(vop2->drm, "%s dst_w[%d] should align as 2 pixel\n",
657 win->data->name, dst_w);
658 dst_w++;
659 }
660 }
661
662 val = vop2_scale_factor(src_w, dst_w);
663 vop2_win_write(win, VOP2_WIN_SCALE_YRGB_X, val);
664 val = vop2_scale_factor(src_h, dst_h);
665 vop2_win_write(win, VOP2_WIN_SCALE_YRGB_Y, val);
666
667 vop2_win_write(win, VOP2_WIN_VSD_YRGB_GT4, gt4);
668 vop2_win_write(win, VOP2_WIN_VSD_YRGB_GT2, gt2);
669
670 vop2_win_write(win, VOP2_WIN_YRGB_HOR_SCL_MODE, hor_scl_mode);
671 vop2_win_write(win, VOP2_WIN_YRGB_VER_SCL_MODE, ver_scl_mode);
672
673 if (vop2_cluster_window(win))
674 return;
675
676 vop2_win_write(win, VOP2_WIN_YRGB_HSCL_FILTER_MODE, hscl_filter_mode);
677 vop2_win_write(win, VOP2_WIN_YRGB_VSCL_FILTER_MODE, vscl_filter_mode);
678
679 if (info->is_yuv) {
680 cbcr_src_w /= info->hsub;
681 cbcr_src_h /= info->vsub;
682
683 gt4 = 0;
684 gt2 = 0;
685
686 if (cbcr_src_h >= (4 * dst_h)) {
687 gt4 = 1;
688 cbcr_src_h >>= 2;
689 } else if (cbcr_src_h >= (2 * dst_h)) {
690 gt2 = 1;
691 cbcr_src_h >>= 1;
692 }
693
694 hor_scl_mode = scl_get_scl_mode(cbcr_src_w, dst_w);
695 ver_scl_mode = scl_get_scl_mode(cbcr_src_h, dst_h);
696
697 val = vop2_scale_factor(cbcr_src_w, dst_w);
698 vop2_win_write(win, VOP2_WIN_SCALE_CBCR_X, val);
699
700 val = vop2_scale_factor(cbcr_src_h, dst_h);
701 vop2_win_write(win, VOP2_WIN_SCALE_CBCR_Y, val);
702
703 vop2_win_write(win, VOP2_WIN_VSD_CBCR_GT4, gt4);
704 vop2_win_write(win, VOP2_WIN_VSD_CBCR_GT2, gt2);
705 vop2_win_write(win, VOP2_WIN_CBCR_HOR_SCL_MODE, hor_scl_mode);
706 vop2_win_write(win, VOP2_WIN_CBCR_VER_SCL_MODE, ver_scl_mode);
707 vop2_win_write(win, VOP2_WIN_CBCR_HSCL_FILTER_MODE, hscl_filter_mode);
708 vop2_win_write(win, VOP2_WIN_CBCR_VSCL_FILTER_MODE, vscl_filter_mode);
709 }
710 }
711
vop2_convert_csc_mode(int csc_mode)712 static int vop2_convert_csc_mode(int csc_mode)
713 {
714 switch (csc_mode) {
715 case V4L2_COLORSPACE_SMPTE170M:
716 case V4L2_COLORSPACE_470_SYSTEM_M:
717 case V4L2_COLORSPACE_470_SYSTEM_BG:
718 return CSC_BT601L;
719 case V4L2_COLORSPACE_REC709:
720 case V4L2_COLORSPACE_SMPTE240M:
721 case V4L2_COLORSPACE_DEFAULT:
722 return CSC_BT709L;
723 case V4L2_COLORSPACE_JPEG:
724 return CSC_BT601F;
725 case V4L2_COLORSPACE_BT2020:
726 return CSC_BT2020;
727 default:
728 return CSC_BT709L;
729 }
730 }
731
732 /*
733 * colorspace path:
734 * Input Win csc Output
735 * 1. YUV(2020) --> Y2R->2020To709->R2Y --> YUV_OUTPUT(601/709)
736 * RGB --> R2Y __/
737 *
738 * 2. YUV(2020) --> bypasss --> YUV_OUTPUT(2020)
739 * RGB --> 709To2020->R2Y __/
740 *
741 * 3. YUV(2020) --> Y2R->2020To709 --> RGB_OUTPUT(709)
742 * RGB --> R2Y __/
743 *
744 * 4. YUV(601/709)-> Y2R->709To2020->R2Y --> YUV_OUTPUT(2020)
745 * RGB --> 709To2020->R2Y __/
746 *
747 * 5. YUV(601/709)-> bypass --> YUV_OUTPUT(709)
748 * RGB --> R2Y __/
749 *
750 * 6. YUV(601/709)-> bypass --> YUV_OUTPUT(601)
751 * RGB --> R2Y(601) __/
752 *
753 * 7. YUV --> Y2R(709) --> RGB_OUTPUT(709)
754 * RGB --> bypass __/
755 *
756 * 8. RGB --> 709To2020->R2Y --> YUV_OUTPUT(2020)
757 *
758 * 9. RGB --> R2Y(709) --> YUV_OUTPUT(709)
759 *
760 * 10. RGB --> R2Y(601) --> YUV_OUTPUT(601)
761 *
762 * 11. RGB --> bypass --> RGB_OUTPUT(709)
763 */
764
vop2_setup_csc_mode(struct vop2_video_port * vp,struct vop2_win * win,struct drm_plane_state * pstate)765 static void vop2_setup_csc_mode(struct vop2_video_port *vp,
766 struct vop2_win *win,
767 struct drm_plane_state *pstate)
768 {
769 struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(vp->crtc.state);
770 int is_input_yuv = pstate->fb->format->is_yuv;
771 int is_output_yuv = is_yuv_output(vcstate->bus_format);
772 int input_csc = V4L2_COLORSPACE_DEFAULT;
773 int output_csc = vcstate->color_space;
774 bool r2y_en, y2r_en;
775 int csc_mode;
776
777 if (is_input_yuv && !is_output_yuv) {
778 y2r_en = true;
779 r2y_en = false;
780 csc_mode = vop2_convert_csc_mode(input_csc);
781 } else if (!is_input_yuv && is_output_yuv) {
782 y2r_en = false;
783 r2y_en = true;
784 csc_mode = vop2_convert_csc_mode(output_csc);
785 } else {
786 y2r_en = false;
787 r2y_en = false;
788 csc_mode = false;
789 }
790
791 vop2_win_write(win, VOP2_WIN_Y2R_EN, y2r_en);
792 vop2_win_write(win, VOP2_WIN_R2Y_EN, r2y_en);
793 vop2_win_write(win, VOP2_WIN_CSC_MODE, csc_mode);
794 }
795
vop2_crtc_enable_irq(struct vop2_video_port * vp,u32 irq)796 static void vop2_crtc_enable_irq(struct vop2_video_port *vp, u32 irq)
797 {
798 struct vop2 *vop2 = vp->vop2;
799
800 vop2_writel(vop2, RK3568_VP_INT_CLR(vp->id), irq << 16 | irq);
801 vop2_writel(vop2, RK3568_VP_INT_EN(vp->id), irq << 16 | irq);
802 }
803
vop2_crtc_disable_irq(struct vop2_video_port * vp,u32 irq)804 static void vop2_crtc_disable_irq(struct vop2_video_port *vp, u32 irq)
805 {
806 struct vop2 *vop2 = vp->vop2;
807
808 vop2_writel(vop2, RK3568_VP_INT_EN(vp->id), irq << 16);
809 }
810
vop2_core_clks_prepare_enable(struct vop2 * vop2)811 static int vop2_core_clks_prepare_enable(struct vop2 *vop2)
812 {
813 int ret;
814
815 ret = clk_prepare_enable(vop2->hclk);
816 if (ret < 0) {
817 drm_err(vop2->drm, "failed to enable hclk - %d\n", ret);
818 return ret;
819 }
820
821 ret = clk_prepare_enable(vop2->aclk);
822 if (ret < 0) {
823 drm_err(vop2->drm, "failed to enable aclk - %d\n", ret);
824 goto err;
825 }
826
827 return 0;
828 err:
829 clk_disable_unprepare(vop2->hclk);
830
831 return ret;
832 }
833
vop2_enable(struct vop2 * vop2)834 static void vop2_enable(struct vop2 *vop2)
835 {
836 int ret;
837
838 ret = pm_runtime_resume_and_get(vop2->dev);
839 if (ret < 0) {
840 drm_err(vop2->drm, "failed to get pm runtime: %d\n", ret);
841 return;
842 }
843
844 ret = vop2_core_clks_prepare_enable(vop2);
845 if (ret) {
846 pm_runtime_put_sync(vop2->dev);
847 return;
848 }
849
850 ret = rockchip_drm_dma_attach_device(vop2->drm, vop2->dev);
851 if (ret) {
852 drm_err(vop2->drm, "failed to attach dma mapping, %d\n", ret);
853 return;
854 }
855
856 regcache_sync(vop2->map);
857
858 if (vop2->data->soc_id == 3566)
859 vop2_writel(vop2, RK3568_OTP_WIN_EN, 1);
860
861 vop2_writel(vop2, RK3568_REG_CFG_DONE, RK3568_REG_CFG_DONE__GLB_CFG_DONE_EN);
862
863 /*
864 * Disable auto gating, this is a workaround to
865 * avoid display image shift when a window enabled.
866 */
867 regmap_clear_bits(vop2->map, RK3568_SYS_AUTO_GATING_CTRL,
868 RK3568_SYS_AUTO_GATING_CTRL__AUTO_GATING_EN);
869
870 vop2_writel(vop2, RK3568_SYS0_INT_CLR,
871 VOP2_INT_BUS_ERRPR << 16 | VOP2_INT_BUS_ERRPR);
872 vop2_writel(vop2, RK3568_SYS0_INT_EN,
873 VOP2_INT_BUS_ERRPR << 16 | VOP2_INT_BUS_ERRPR);
874 vop2_writel(vop2, RK3568_SYS1_INT_CLR,
875 VOP2_INT_BUS_ERRPR << 16 | VOP2_INT_BUS_ERRPR);
876 vop2_writel(vop2, RK3568_SYS1_INT_EN,
877 VOP2_INT_BUS_ERRPR << 16 | VOP2_INT_BUS_ERRPR);
878 }
879
vop2_disable(struct vop2 * vop2)880 static void vop2_disable(struct vop2 *vop2)
881 {
882 rockchip_drm_dma_detach_device(vop2->drm, vop2->dev);
883
884 pm_runtime_put_sync(vop2->dev);
885
886 regcache_mark_dirty(vop2->map);
887
888 clk_disable_unprepare(vop2->aclk);
889 clk_disable_unprepare(vop2->hclk);
890 }
891
vop2_crtc_atomic_disable(struct drm_crtc * crtc,struct drm_atomic_state * state)892 static void vop2_crtc_atomic_disable(struct drm_crtc *crtc,
893 struct drm_atomic_state *state)
894 {
895 struct vop2_video_port *vp = to_vop2_video_port(crtc);
896 struct vop2 *vop2 = vp->vop2;
897 struct drm_crtc_state *old_crtc_state;
898 int ret;
899
900 vop2_lock(vop2);
901
902 old_crtc_state = drm_atomic_get_old_crtc_state(state, crtc);
903 drm_atomic_helper_disable_planes_on_crtc(old_crtc_state, false);
904
905 drm_crtc_vblank_off(crtc);
906
907 /*
908 * Vop standby will take effect at end of current frame,
909 * if dsp hold valid irq happen, it means standby complete.
910 *
911 * we must wait standby complete when we want to disable aclk,
912 * if not, memory bus maybe dead.
913 */
914 reinit_completion(&vp->dsp_hold_completion);
915
916 vop2_crtc_enable_irq(vp, VP_INT_DSP_HOLD_VALID);
917
918 vop2_vp_write(vp, RK3568_VP_DSP_CTRL, RK3568_VP_DSP_CTRL__STANDBY);
919
920 ret = wait_for_completion_timeout(&vp->dsp_hold_completion,
921 msecs_to_jiffies(50));
922 if (!ret)
923 drm_info(vop2->drm, "wait for vp%d dsp_hold timeout\n", vp->id);
924
925 vop2_crtc_disable_irq(vp, VP_INT_DSP_HOLD_VALID);
926
927 clk_disable_unprepare(vp->dclk);
928
929 vop2->enable_count--;
930
931 if (!vop2->enable_count)
932 vop2_disable(vop2);
933
934 vop2_unlock(vop2);
935
936 if (crtc->state->event && !crtc->state->active) {
937 spin_lock_irq(&crtc->dev->event_lock);
938 drm_crtc_send_vblank_event(crtc, crtc->state->event);
939 spin_unlock_irq(&crtc->dev->event_lock);
940
941 crtc->state->event = NULL;
942 }
943 }
944
vop2_plane_atomic_check(struct drm_plane * plane,struct drm_atomic_state * astate)945 static int vop2_plane_atomic_check(struct drm_plane *plane,
946 struct drm_atomic_state *astate)
947 {
948 struct drm_plane_state *pstate = drm_atomic_get_new_plane_state(astate, plane);
949 struct drm_framebuffer *fb = pstate->fb;
950 struct drm_crtc *crtc = pstate->crtc;
951 struct drm_crtc_state *cstate;
952 struct vop2_video_port *vp;
953 struct vop2 *vop2;
954 const struct vop2_data *vop2_data;
955 struct drm_rect *dest = &pstate->dst;
956 struct drm_rect *src = &pstate->src;
957 int min_scale = FRAC_16_16(1, 8);
958 int max_scale = FRAC_16_16(8, 1);
959 int format;
960 int ret;
961
962 if (!crtc)
963 return 0;
964
965 vp = to_vop2_video_port(crtc);
966 vop2 = vp->vop2;
967 vop2_data = vop2->data;
968
969 cstate = drm_atomic_get_existing_crtc_state(pstate->state, crtc);
970 if (WARN_ON(!cstate))
971 return -EINVAL;
972
973 ret = drm_atomic_helper_check_plane_state(pstate, cstate,
974 min_scale, max_scale,
975 true, true);
976 if (ret)
977 return ret;
978
979 if (!pstate->visible)
980 return 0;
981
982 format = vop2_convert_format(fb->format->format);
983 if (format < 0)
984 return format;
985
986 if (drm_rect_width(src) >> 16 < 4 || drm_rect_height(src) >> 16 < 4 ||
987 drm_rect_width(dest) < 4 || drm_rect_width(dest) < 4) {
988 drm_err(vop2->drm, "Invalid size: %dx%d->%dx%d, min size is 4x4\n",
989 drm_rect_width(src) >> 16, drm_rect_height(src) >> 16,
990 drm_rect_width(dest), drm_rect_height(dest));
991 pstate->visible = false;
992 return 0;
993 }
994
995 if (drm_rect_width(src) >> 16 > vop2_data->max_input.width ||
996 drm_rect_height(src) >> 16 > vop2_data->max_input.height) {
997 drm_err(vop2->drm, "Invalid source: %dx%d. max input: %dx%d\n",
998 drm_rect_width(src) >> 16,
999 drm_rect_height(src) >> 16,
1000 vop2_data->max_input.width,
1001 vop2_data->max_input.height);
1002 return -EINVAL;
1003 }
1004
1005 /*
1006 * Src.x1 can be odd when do clip, but yuv plane start point
1007 * need align with 2 pixel.
1008 */
1009 if (fb->format->is_yuv && ((pstate->src.x1 >> 16) % 2)) {
1010 drm_err(vop2->drm, "Invalid Source: Yuv format not support odd xpos\n");
1011 return -EINVAL;
1012 }
1013
1014 return 0;
1015 }
1016
vop2_plane_atomic_disable(struct drm_plane * plane,struct drm_atomic_state * state)1017 static void vop2_plane_atomic_disable(struct drm_plane *plane,
1018 struct drm_atomic_state *state)
1019 {
1020 struct drm_plane_state *old_pstate = NULL;
1021 struct vop2_win *win = to_vop2_win(plane);
1022 struct vop2 *vop2 = win->vop2;
1023
1024 drm_dbg(vop2->drm, "%s disable\n", win->data->name);
1025
1026 if (state)
1027 old_pstate = drm_atomic_get_old_plane_state(state, plane);
1028 if (old_pstate && !old_pstate->crtc)
1029 return;
1030
1031 vop2_win_disable(win);
1032 vop2_win_write(win, VOP2_WIN_YUV_CLIP, 0);
1033 }
1034
1035 /*
1036 * The color key is 10 bit, so all format should
1037 * convert to 10 bit here.
1038 */
vop2_plane_setup_color_key(struct drm_plane * plane,u32 color_key)1039 static void vop2_plane_setup_color_key(struct drm_plane *plane, u32 color_key)
1040 {
1041 struct drm_plane_state *pstate = plane->state;
1042 struct drm_framebuffer *fb = pstate->fb;
1043 struct vop2_win *win = to_vop2_win(plane);
1044 u32 color_key_en = 0;
1045 u32 r = 0;
1046 u32 g = 0;
1047 u32 b = 0;
1048
1049 if (!(color_key & VOP2_COLOR_KEY_MASK) || fb->format->is_yuv) {
1050 vop2_win_write(win, VOP2_WIN_COLOR_KEY_EN, 0);
1051 return;
1052 }
1053
1054 switch (fb->format->format) {
1055 case DRM_FORMAT_RGB565:
1056 case DRM_FORMAT_BGR565:
1057 r = (color_key & 0xf800) >> 11;
1058 g = (color_key & 0x7e0) >> 5;
1059 b = (color_key & 0x1f);
1060 r <<= 5;
1061 g <<= 4;
1062 b <<= 5;
1063 color_key_en = 1;
1064 break;
1065 case DRM_FORMAT_XRGB8888:
1066 case DRM_FORMAT_ARGB8888:
1067 case DRM_FORMAT_XBGR8888:
1068 case DRM_FORMAT_ABGR8888:
1069 case DRM_FORMAT_RGB888:
1070 case DRM_FORMAT_BGR888:
1071 r = (color_key & 0xff0000) >> 16;
1072 g = (color_key & 0xff00) >> 8;
1073 b = (color_key & 0xff);
1074 r <<= 2;
1075 g <<= 2;
1076 b <<= 2;
1077 color_key_en = 1;
1078 break;
1079 }
1080
1081 vop2_win_write(win, VOP2_WIN_COLOR_KEY_EN, color_key_en);
1082 vop2_win_write(win, VOP2_WIN_COLOR_KEY, (r << 20) | (g << 10) | b);
1083 }
1084
vop2_plane_atomic_update(struct drm_plane * plane,struct drm_atomic_state * state)1085 static void vop2_plane_atomic_update(struct drm_plane *plane,
1086 struct drm_atomic_state *state)
1087 {
1088 struct drm_plane_state *pstate = plane->state;
1089 struct drm_crtc *crtc = pstate->crtc;
1090 struct vop2_win *win = to_vop2_win(plane);
1091 struct vop2_video_port *vp = to_vop2_video_port(crtc);
1092 struct drm_display_mode *adjusted_mode = &crtc->state->adjusted_mode;
1093 struct vop2 *vop2 = win->vop2;
1094 struct drm_framebuffer *fb = pstate->fb;
1095 u32 bpp = fb->format->cpp[0] * 8;
1096 u32 actual_w, actual_h, dsp_w, dsp_h;
1097 u32 act_info, dsp_info;
1098 u32 format;
1099 u32 afbc_format;
1100 u32 rb_swap;
1101 u32 uv_swap;
1102 struct drm_rect *src = &pstate->src;
1103 struct drm_rect *dest = &pstate->dst;
1104 u32 afbc_tile_num;
1105 u32 transform_offset;
1106 bool dither_up;
1107 bool xmirror = pstate->rotation & DRM_MODE_REFLECT_X ? true : false;
1108 bool ymirror = pstate->rotation & DRM_MODE_REFLECT_Y ? true : false;
1109 bool rotate_270 = pstate->rotation & DRM_MODE_ROTATE_270;
1110 bool rotate_90 = pstate->rotation & DRM_MODE_ROTATE_90;
1111 struct rockchip_gem_object *rk_obj;
1112 unsigned long offset;
1113 bool afbc_en;
1114 dma_addr_t yrgb_mst;
1115 dma_addr_t uv_mst;
1116
1117 /*
1118 * can't update plane when vop2 is disabled.
1119 */
1120 if (WARN_ON(!crtc))
1121 return;
1122
1123 if (!pstate->visible) {
1124 vop2_plane_atomic_disable(plane, state);
1125 return;
1126 }
1127
1128 afbc_en = rockchip_afbc(plane, fb->modifier);
1129
1130 offset = (src->x1 >> 16) * fb->format->cpp[0];
1131
1132 /*
1133 * AFBC HDR_PTR must set to the zero offset of the framebuffer.
1134 */
1135 if (afbc_en)
1136 offset = 0;
1137 else if (pstate->rotation & DRM_MODE_REFLECT_Y)
1138 offset += ((src->y2 >> 16) - 1) * fb->pitches[0];
1139 else
1140 offset += (src->y1 >> 16) * fb->pitches[0];
1141
1142 rk_obj = to_rockchip_obj(fb->obj[0]);
1143
1144 yrgb_mst = rk_obj->dma_addr + offset + fb->offsets[0];
1145 if (fb->format->is_yuv) {
1146 int hsub = fb->format->hsub;
1147 int vsub = fb->format->vsub;
1148
1149 offset = (src->x1 >> 16) * fb->format->cpp[1] / hsub;
1150 offset += (src->y1 >> 16) * fb->pitches[1] / vsub;
1151
1152 if ((pstate->rotation & DRM_MODE_REFLECT_Y) && !afbc_en)
1153 offset += fb->pitches[1] * ((pstate->src_h >> 16) - 2) / vsub;
1154
1155 rk_obj = to_rockchip_obj(fb->obj[0]);
1156 uv_mst = rk_obj->dma_addr + offset + fb->offsets[1];
1157 }
1158
1159 actual_w = drm_rect_width(src) >> 16;
1160 actual_h = drm_rect_height(src) >> 16;
1161 dsp_w = drm_rect_width(dest);
1162
1163 if (dest->x1 + dsp_w > adjusted_mode->hdisplay) {
1164 drm_err(vop2->drm, "vp%d %s dest->x1[%d] + dsp_w[%d] exceed mode hdisplay[%d]\n",
1165 vp->id, win->data->name, dest->x1, dsp_w, adjusted_mode->hdisplay);
1166 dsp_w = adjusted_mode->hdisplay - dest->x1;
1167 if (dsp_w < 4)
1168 dsp_w = 4;
1169 actual_w = dsp_w * actual_w / drm_rect_width(dest);
1170 }
1171
1172 dsp_h = drm_rect_height(dest);
1173
1174 if (dest->y1 + dsp_h > adjusted_mode->vdisplay) {
1175 drm_err(vop2->drm, "vp%d %s dest->y1[%d] + dsp_h[%d] exceed mode vdisplay[%d]\n",
1176 vp->id, win->data->name, dest->y1, dsp_h, adjusted_mode->vdisplay);
1177 dsp_h = adjusted_mode->vdisplay - dest->y1;
1178 if (dsp_h < 4)
1179 dsp_h = 4;
1180 actual_h = dsp_h * actual_h / drm_rect_height(dest);
1181 }
1182
1183 /*
1184 * This is workaround solution for IC design:
1185 * esmart can't support scale down when actual_w % 16 == 1.
1186 */
1187 if (!(win->data->feature & WIN_FEATURE_AFBDC)) {
1188 if (actual_w > dsp_w && (actual_w & 0xf) == 1) {
1189 drm_err(vop2->drm, "vp%d %s act_w[%d] MODE 16 == 1\n",
1190 vp->id, win->data->name, actual_w);
1191 actual_w -= 1;
1192 }
1193 }
1194
1195 if (afbc_en && actual_w % 4) {
1196 drm_err(vop2->drm, "vp%d %s actual_w[%d] not 4 pixel aligned\n",
1197 vp->id, win->data->name, actual_w);
1198 actual_w = ALIGN_DOWN(actual_w, 4);
1199 }
1200
1201 act_info = (actual_h - 1) << 16 | ((actual_w - 1) & 0xffff);
1202 dsp_info = (dsp_h - 1) << 16 | ((dsp_w - 1) & 0xffff);
1203
1204 format = vop2_convert_format(fb->format->format);
1205
1206 drm_dbg(vop2->drm, "vp%d update %s[%dx%d->%dx%d@%dx%d] fmt[%p4cc_%s] addr[%pad]\n",
1207 vp->id, win->data->name, actual_w, actual_h, dsp_w, dsp_h,
1208 dest->x1, dest->y1,
1209 &fb->format->format,
1210 afbc_en ? "AFBC" : "", &yrgb_mst);
1211
1212 if (afbc_en) {
1213 u32 stride;
1214
1215 /* the afbc superblock is 16 x 16 */
1216 afbc_format = vop2_convert_afbc_format(fb->format->format);
1217
1218 /* Enable color transform for YTR */
1219 if (fb->modifier & AFBC_FORMAT_MOD_YTR)
1220 afbc_format |= (1 << 4);
1221
1222 afbc_tile_num = ALIGN(actual_w, 16) >> 4;
1223
1224 /*
1225 * AFBC pic_vir_width is count by pixel, this is different
1226 * with WIN_VIR_STRIDE.
1227 */
1228 stride = (fb->pitches[0] << 3) / bpp;
1229 if ((stride & 0x3f) && (xmirror || rotate_90 || rotate_270))
1230 drm_err(vop2->drm, "vp%d %s stride[%d] not 64 pixel aligned\n",
1231 vp->id, win->data->name, stride);
1232
1233 rb_swap = vop2_afbc_rb_swap(fb->format->format);
1234 uv_swap = vop2_afbc_uv_swap(fb->format->format);
1235 /*
1236 * This is a workaround for crazy IC design, Cluster
1237 * and Esmart/Smart use different format configuration map:
1238 * YUV420_10BIT: 0x10 for Cluster, 0x14 for Esmart/Smart.
1239 *
1240 * This is one thing we can make the convert simple:
1241 * AFBCD decode all the YUV data to YUV444. So we just
1242 * set all the yuv 10 bit to YUV444_10.
1243 */
1244 if (fb->format->is_yuv && bpp == 10)
1245 format = VOP2_CLUSTER_YUV444_10;
1246
1247 if (vop2_cluster_window(win))
1248 vop2_win_write(win, VOP2_WIN_AFBC_ENABLE, 1);
1249 vop2_win_write(win, VOP2_WIN_AFBC_FORMAT, afbc_format);
1250 vop2_win_write(win, VOP2_WIN_AFBC_RB_SWAP, rb_swap);
1251 vop2_win_write(win, VOP2_WIN_AFBC_UV_SWAP, uv_swap);
1252 vop2_win_write(win, VOP2_WIN_AFBC_AUTO_GATING_EN, 0);
1253 vop2_win_write(win, VOP2_WIN_AFBC_BLOCK_SPLIT_EN, 0);
1254 if (pstate->rotation & (DRM_MODE_ROTATE_270 | DRM_MODE_ROTATE_90)) {
1255 vop2_win_write(win, VOP2_WIN_AFBC_HALF_BLOCK_EN, 0);
1256 transform_offset = vop2_afbc_transform_offset(pstate, false);
1257 } else {
1258 vop2_win_write(win, VOP2_WIN_AFBC_HALF_BLOCK_EN, 1);
1259 transform_offset = vop2_afbc_transform_offset(pstate, true);
1260 }
1261 vop2_win_write(win, VOP2_WIN_AFBC_HDR_PTR, yrgb_mst);
1262 vop2_win_write(win, VOP2_WIN_AFBC_PIC_SIZE, act_info);
1263 vop2_win_write(win, VOP2_WIN_AFBC_TRANSFORM_OFFSET, transform_offset);
1264 vop2_win_write(win, VOP2_WIN_AFBC_PIC_OFFSET, ((src->x1 >> 16) | src->y1));
1265 vop2_win_write(win, VOP2_WIN_AFBC_DSP_OFFSET, (dest->x1 | (dest->y1 << 16)));
1266 vop2_win_write(win, VOP2_WIN_AFBC_PIC_VIR_WIDTH, stride);
1267 vop2_win_write(win, VOP2_WIN_AFBC_TILE_NUM, afbc_tile_num);
1268 vop2_win_write(win, VOP2_WIN_XMIRROR, xmirror);
1269 vop2_win_write(win, VOP2_WIN_AFBC_ROTATE_270, rotate_270);
1270 vop2_win_write(win, VOP2_WIN_AFBC_ROTATE_90, rotate_90);
1271 } else {
1272 if (vop2_cluster_window(win)) {
1273 vop2_win_write(win, VOP2_WIN_AFBC_ENABLE, 0);
1274 vop2_win_write(win, VOP2_WIN_AFBC_TRANSFORM_OFFSET, 0);
1275 }
1276
1277 vop2_win_write(win, VOP2_WIN_YRGB_VIR, DIV_ROUND_UP(fb->pitches[0], 4));
1278 }
1279
1280 vop2_win_write(win, VOP2_WIN_YMIRROR, ymirror);
1281
1282 if (rotate_90 || rotate_270) {
1283 act_info = swahw32(act_info);
1284 actual_w = drm_rect_height(src) >> 16;
1285 actual_h = drm_rect_width(src) >> 16;
1286 }
1287
1288 vop2_win_write(win, VOP2_WIN_FORMAT, format);
1289 vop2_win_write(win, VOP2_WIN_YRGB_MST, yrgb_mst);
1290
1291 rb_swap = vop2_win_rb_swap(fb->format->format);
1292 vop2_win_write(win, VOP2_WIN_RB_SWAP, rb_swap);
1293 if (!vop2_cluster_window(win)) {
1294 uv_swap = vop2_win_uv_swap(fb->format->format);
1295 vop2_win_write(win, VOP2_WIN_UV_SWAP, uv_swap);
1296 }
1297
1298 if (fb->format->is_yuv) {
1299 vop2_win_write(win, VOP2_WIN_UV_VIR, DIV_ROUND_UP(fb->pitches[1], 4));
1300 vop2_win_write(win, VOP2_WIN_UV_MST, uv_mst);
1301 }
1302
1303 vop2_setup_scale(vop2, win, actual_w, actual_h, dsp_w, dsp_h, fb->format->format);
1304 if (!vop2_cluster_window(win))
1305 vop2_plane_setup_color_key(plane, 0);
1306 vop2_win_write(win, VOP2_WIN_ACT_INFO, act_info);
1307 vop2_win_write(win, VOP2_WIN_DSP_INFO, dsp_info);
1308 vop2_win_write(win, VOP2_WIN_DSP_ST, dest->y1 << 16 | (dest->x1 & 0xffff));
1309
1310 vop2_setup_csc_mode(vp, win, pstate);
1311
1312 dither_up = vop2_win_dither_up(fb->format->format);
1313 vop2_win_write(win, VOP2_WIN_DITHER_UP, dither_up);
1314
1315 vop2_win_write(win, VOP2_WIN_ENABLE, 1);
1316
1317 if (vop2_cluster_window(win)) {
1318 int lb_mode = vop2_get_cluster_lb_mode(win, pstate);
1319
1320 vop2_win_write(win, VOP2_WIN_CLUSTER_LB_MODE, lb_mode);
1321 vop2_win_write(win, VOP2_WIN_CLUSTER_ENABLE, 1);
1322 }
1323 }
1324
1325 static const struct drm_plane_helper_funcs vop2_plane_helper_funcs = {
1326 .atomic_check = vop2_plane_atomic_check,
1327 .atomic_update = vop2_plane_atomic_update,
1328 .atomic_disable = vop2_plane_atomic_disable,
1329 };
1330
1331 static const struct drm_plane_funcs vop2_plane_funcs = {
1332 .update_plane = drm_atomic_helper_update_plane,
1333 .disable_plane = drm_atomic_helper_disable_plane,
1334 .destroy = drm_plane_cleanup,
1335 .reset = drm_atomic_helper_plane_reset,
1336 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
1337 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
1338 .format_mod_supported = rockchip_vop2_mod_supported,
1339 };
1340
vop2_crtc_enable_vblank(struct drm_crtc * crtc)1341 static int vop2_crtc_enable_vblank(struct drm_crtc *crtc)
1342 {
1343 struct vop2_video_port *vp = to_vop2_video_port(crtc);
1344
1345 vop2_crtc_enable_irq(vp, VP_INT_FS_FIELD);
1346
1347 return 0;
1348 }
1349
vop2_crtc_disable_vblank(struct drm_crtc * crtc)1350 static void vop2_crtc_disable_vblank(struct drm_crtc *crtc)
1351 {
1352 struct vop2_video_port *vp = to_vop2_video_port(crtc);
1353
1354 vop2_crtc_disable_irq(vp, VP_INT_FS_FIELD);
1355 }
1356
vop2_crtc_mode_fixup(struct drm_crtc * crtc,const struct drm_display_mode * mode,struct drm_display_mode * adj_mode)1357 static bool vop2_crtc_mode_fixup(struct drm_crtc *crtc,
1358 const struct drm_display_mode *mode,
1359 struct drm_display_mode *adj_mode)
1360 {
1361 drm_mode_set_crtcinfo(adj_mode, CRTC_INTERLACE_HALVE_V |
1362 CRTC_STEREO_DOUBLE);
1363
1364 return true;
1365 }
1366
vop2_dither_setup(struct drm_crtc * crtc,u32 * dsp_ctrl)1367 static void vop2_dither_setup(struct drm_crtc *crtc, u32 *dsp_ctrl)
1368 {
1369 struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
1370
1371 switch (vcstate->bus_format) {
1372 case MEDIA_BUS_FMT_RGB565_1X16:
1373 *dsp_ctrl |= RK3568_VP_DSP_CTRL__DITHER_DOWN_EN;
1374 break;
1375 case MEDIA_BUS_FMT_RGB666_1X18:
1376 case MEDIA_BUS_FMT_RGB666_1X24_CPADHI:
1377 case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
1378 *dsp_ctrl |= RK3568_VP_DSP_CTRL__DITHER_DOWN_EN;
1379 *dsp_ctrl |= RGB888_TO_RGB666;
1380 break;
1381 case MEDIA_BUS_FMT_YUV8_1X24:
1382 case MEDIA_BUS_FMT_UYYVYY8_0_5X24:
1383 *dsp_ctrl |= RK3568_VP_DSP_CTRL__PRE_DITHER_DOWN_EN;
1384 break;
1385 default:
1386 break;
1387 }
1388
1389 if (vcstate->output_mode != ROCKCHIP_OUT_MODE_AAAA)
1390 *dsp_ctrl |= RK3568_VP_DSP_CTRL__PRE_DITHER_DOWN_EN;
1391
1392 *dsp_ctrl |= FIELD_PREP(RK3568_VP_DSP_CTRL__DITHER_DOWN_SEL,
1393 DITHER_DOWN_ALLEGRO);
1394 }
1395
vop2_post_config(struct drm_crtc * crtc)1396 static void vop2_post_config(struct drm_crtc *crtc)
1397 {
1398 struct vop2_video_port *vp = to_vop2_video_port(crtc);
1399 struct drm_display_mode *mode = &crtc->state->adjusted_mode;
1400 u16 vtotal = mode->crtc_vtotal;
1401 u16 hdisplay = mode->crtc_hdisplay;
1402 u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start;
1403 u16 vdisplay = mode->crtc_vdisplay;
1404 u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start;
1405 u32 left_margin = 100, right_margin = 100;
1406 u32 top_margin = 100, bottom_margin = 100;
1407 u16 hsize = hdisplay * (left_margin + right_margin) / 200;
1408 u16 vsize = vdisplay * (top_margin + bottom_margin) / 200;
1409 u16 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
1410 u16 hact_end, vact_end;
1411 u32 val;
1412 u32 bg_dly;
1413 u32 pre_scan_dly;
1414
1415 bg_dly = vp->data->pre_scan_max_dly[3];
1416 vop2_writel(vp->vop2, RK3568_VP_BG_MIX_CTRL(vp->id),
1417 FIELD_PREP(RK3568_VP_BG_MIX_CTRL__BG_DLY, bg_dly));
1418
1419 pre_scan_dly = ((bg_dly + (hdisplay >> 1) - 1) << 16) | hsync_len;
1420 vop2_vp_write(vp, RK3568_VP_PRE_SCAN_HTIMING, pre_scan_dly);
1421
1422 vsize = rounddown(vsize, 2);
1423 hsize = rounddown(hsize, 2);
1424 hact_st += hdisplay * (100 - left_margin) / 200;
1425 hact_end = hact_st + hsize;
1426 val = hact_st << 16;
1427 val |= hact_end;
1428 vop2_vp_write(vp, RK3568_VP_POST_DSP_HACT_INFO, val);
1429 vact_st += vdisplay * (100 - top_margin) / 200;
1430 vact_end = vact_st + vsize;
1431 val = vact_st << 16;
1432 val |= vact_end;
1433 vop2_vp_write(vp, RK3568_VP_POST_DSP_VACT_INFO, val);
1434 val = scl_cal_scale2(vdisplay, vsize) << 16;
1435 val |= scl_cal_scale2(hdisplay, hsize);
1436 vop2_vp_write(vp, RK3568_VP_POST_SCL_FACTOR_YRGB, val);
1437
1438 val = 0;
1439 if (hdisplay != hsize)
1440 val |= RK3568_VP_POST_SCL_CTRL__HSCALEDOWN;
1441 if (vdisplay != vsize)
1442 val |= RK3568_VP_POST_SCL_CTRL__VSCALEDOWN;
1443 vop2_vp_write(vp, RK3568_VP_POST_SCL_CTRL, val);
1444
1445 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1446 u16 vact_st_f1 = vtotal + vact_st + 1;
1447 u16 vact_end_f1 = vact_st_f1 + vsize;
1448
1449 val = vact_st_f1 << 16 | vact_end_f1;
1450 vop2_vp_write(vp, RK3568_VP_POST_DSP_VACT_INFO_F1, val);
1451 }
1452
1453 vop2_vp_write(vp, RK3568_VP_DSP_BG, 0);
1454 }
1455
rk3568_set_intf_mux(struct vop2_video_port * vp,int id,u32 polflags)1456 static void rk3568_set_intf_mux(struct vop2_video_port *vp, int id,
1457 u32 polflags)
1458 {
1459 struct vop2 *vop2 = vp->vop2;
1460 u32 die, dip;
1461
1462 die = vop2_readl(vop2, RK3568_DSP_IF_EN);
1463 dip = vop2_readl(vop2, RK3568_DSP_IF_POL);
1464
1465 switch (id) {
1466 case ROCKCHIP_VOP2_EP_RGB0:
1467 die &= ~RK3568_SYS_DSP_INFACE_EN_RGB_MUX;
1468 die |= RK3568_SYS_DSP_INFACE_EN_RGB |
1469 FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_RGB_MUX, vp->id);
1470 dip &= ~RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL;
1471 dip |= FIELD_PREP(RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL, polflags);
1472 if (polflags & POLFLAG_DCLK_INV)
1473 regmap_write(vop2->grf, RK3568_GRF_VO_CON1, BIT(3 + 16) | BIT(3));
1474 else
1475 regmap_write(vop2->grf, RK3568_GRF_VO_CON1, BIT(3 + 16));
1476 break;
1477 case ROCKCHIP_VOP2_EP_HDMI0:
1478 die &= ~RK3568_SYS_DSP_INFACE_EN_HDMI_MUX;
1479 die |= RK3568_SYS_DSP_INFACE_EN_HDMI |
1480 FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_HDMI_MUX, vp->id);
1481 dip &= ~RK3568_DSP_IF_POL__HDMI_PIN_POL;
1482 dip |= FIELD_PREP(RK3568_DSP_IF_POL__HDMI_PIN_POL, polflags);
1483 break;
1484 case ROCKCHIP_VOP2_EP_EDP0:
1485 die &= ~RK3568_SYS_DSP_INFACE_EN_EDP_MUX;
1486 die |= RK3568_SYS_DSP_INFACE_EN_EDP |
1487 FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_EDP_MUX, vp->id);
1488 dip &= ~RK3568_DSP_IF_POL__EDP_PIN_POL;
1489 dip |= FIELD_PREP(RK3568_DSP_IF_POL__EDP_PIN_POL, polflags);
1490 break;
1491 case ROCKCHIP_VOP2_EP_MIPI0:
1492 die &= ~RK3568_SYS_DSP_INFACE_EN_MIPI0_MUX;
1493 die |= RK3568_SYS_DSP_INFACE_EN_MIPI0 |
1494 FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_MIPI0_MUX, vp->id);
1495 dip &= ~RK3568_DSP_IF_POL__MIPI_PIN_POL;
1496 dip |= FIELD_PREP(RK3568_DSP_IF_POL__MIPI_PIN_POL, polflags);
1497 break;
1498 case ROCKCHIP_VOP2_EP_MIPI1:
1499 die &= ~RK3568_SYS_DSP_INFACE_EN_MIPI1_MUX;
1500 die |= RK3568_SYS_DSP_INFACE_EN_MIPI1 |
1501 FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_MIPI1_MUX, vp->id);
1502 dip &= ~RK3568_DSP_IF_POL__MIPI_PIN_POL;
1503 dip |= FIELD_PREP(RK3568_DSP_IF_POL__MIPI_PIN_POL, polflags);
1504 break;
1505 case ROCKCHIP_VOP2_EP_LVDS0:
1506 die &= ~RK3568_SYS_DSP_INFACE_EN_LVDS0_MUX;
1507 die |= RK3568_SYS_DSP_INFACE_EN_LVDS0 |
1508 FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_LVDS0_MUX, vp->id);
1509 dip &= ~RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL;
1510 dip |= FIELD_PREP(RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL, polflags);
1511 break;
1512 case ROCKCHIP_VOP2_EP_LVDS1:
1513 die &= ~RK3568_SYS_DSP_INFACE_EN_LVDS1_MUX;
1514 die |= RK3568_SYS_DSP_INFACE_EN_LVDS1 |
1515 FIELD_PREP(RK3568_SYS_DSP_INFACE_EN_LVDS1_MUX, vp->id);
1516 dip &= ~RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL;
1517 dip |= FIELD_PREP(RK3568_DSP_IF_POL__RGB_LVDS_PIN_POL, polflags);
1518 break;
1519 default:
1520 drm_err(vop2->drm, "Invalid interface id %d on vp%d\n", id, vp->id);
1521 return;
1522 }
1523
1524 dip |= RK3568_DSP_IF_POL__CFG_DONE_IMD;
1525
1526 vop2_writel(vop2, RK3568_DSP_IF_EN, die);
1527 vop2_writel(vop2, RK3568_DSP_IF_POL, dip);
1528 }
1529
us_to_vertical_line(struct drm_display_mode * mode,int us)1530 static int us_to_vertical_line(struct drm_display_mode *mode, int us)
1531 {
1532 return us * mode->clock / mode->htotal / 1000;
1533 }
1534
vop2_crtc_atomic_enable(struct drm_crtc * crtc,struct drm_atomic_state * state)1535 static void vop2_crtc_atomic_enable(struct drm_crtc *crtc,
1536 struct drm_atomic_state *state)
1537 {
1538 struct vop2_video_port *vp = to_vop2_video_port(crtc);
1539 struct vop2 *vop2 = vp->vop2;
1540 const struct vop2_data *vop2_data = vop2->data;
1541 const struct vop2_video_port_data *vp_data = &vop2_data->vp[vp->id];
1542 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
1543 struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(crtc->state);
1544 struct drm_display_mode *mode = &crtc->state->adjusted_mode;
1545 unsigned long clock = mode->crtc_clock * 1000;
1546 u16 hsync_len = mode->crtc_hsync_end - mode->crtc_hsync_start;
1547 u16 hdisplay = mode->crtc_hdisplay;
1548 u16 htotal = mode->crtc_htotal;
1549 u16 hact_st = mode->crtc_htotal - mode->crtc_hsync_start;
1550 u16 hact_end = hact_st + hdisplay;
1551 u16 vdisplay = mode->crtc_vdisplay;
1552 u16 vtotal = mode->crtc_vtotal;
1553 u16 vsync_len = mode->crtc_vsync_end - mode->crtc_vsync_start;
1554 u16 vact_st = mode->crtc_vtotal - mode->crtc_vsync_start;
1555 u16 vact_end = vact_st + vdisplay;
1556 u8 out_mode;
1557 u32 dsp_ctrl = 0;
1558 int act_end;
1559 u32 val, polflags;
1560 int ret;
1561 struct drm_encoder *encoder;
1562
1563 drm_dbg(vop2->drm, "Update mode to %dx%d%s%d, type: %d for vp%d\n",
1564 hdisplay, vdisplay, mode->flags & DRM_MODE_FLAG_INTERLACE ? "i" : "p",
1565 drm_mode_vrefresh(mode), vcstate->output_type, vp->id);
1566
1567 vop2_lock(vop2);
1568
1569 ret = clk_prepare_enable(vp->dclk);
1570 if (ret < 0) {
1571 drm_err(vop2->drm, "failed to enable dclk for video port%d - %d\n",
1572 vp->id, ret);
1573 vop2_unlock(vop2);
1574 return;
1575 }
1576
1577 if (!vop2->enable_count)
1578 vop2_enable(vop2);
1579
1580 vop2->enable_count++;
1581
1582 vcstate->yuv_overlay = is_yuv_output(vcstate->bus_format);
1583
1584 vop2_crtc_enable_irq(vp, VP_INT_POST_BUF_EMPTY);
1585
1586 polflags = 0;
1587 if (vcstate->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE)
1588 polflags |= POLFLAG_DCLK_INV;
1589 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
1590 polflags |= BIT(HSYNC_POSITIVE);
1591 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
1592 polflags |= BIT(VSYNC_POSITIVE);
1593
1594 drm_for_each_encoder_mask(encoder, crtc->dev, crtc_state->encoder_mask) {
1595 struct rockchip_encoder *rkencoder = to_rockchip_encoder(encoder);
1596
1597 rk3568_set_intf_mux(vp, rkencoder->crtc_endpoint_id, polflags);
1598 }
1599
1600 if (vcstate->output_mode == ROCKCHIP_OUT_MODE_AAAA &&
1601 !(vp_data->feature & VOP_FEATURE_OUTPUT_10BIT))
1602 out_mode = ROCKCHIP_OUT_MODE_P888;
1603 else
1604 out_mode = vcstate->output_mode;
1605
1606 dsp_ctrl |= FIELD_PREP(RK3568_VP_DSP_CTRL__OUT_MODE, out_mode);
1607
1608 if (vop2_output_uv_swap(vcstate->bus_format, vcstate->output_mode))
1609 dsp_ctrl |= RK3568_VP_DSP_CTRL__DSP_RB_SWAP;
1610
1611 if (vcstate->yuv_overlay)
1612 dsp_ctrl |= RK3568_VP_DSP_CTRL__POST_DSP_OUT_R2Y;
1613
1614 vop2_dither_setup(crtc, &dsp_ctrl);
1615
1616 vop2_vp_write(vp, RK3568_VP_DSP_HTOTAL_HS_END, (htotal << 16) | hsync_len);
1617 val = hact_st << 16;
1618 val |= hact_end;
1619 vop2_vp_write(vp, RK3568_VP_DSP_HACT_ST_END, val);
1620
1621 val = vact_st << 16;
1622 val |= vact_end;
1623 vop2_vp_write(vp, RK3568_VP_DSP_VACT_ST_END, val);
1624
1625 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
1626 u16 vact_st_f1 = vtotal + vact_st + 1;
1627 u16 vact_end_f1 = vact_st_f1 + vdisplay;
1628
1629 val = vact_st_f1 << 16 | vact_end_f1;
1630 vop2_vp_write(vp, RK3568_VP_DSP_VACT_ST_END_F1, val);
1631
1632 val = vtotal << 16 | (vtotal + vsync_len);
1633 vop2_vp_write(vp, RK3568_VP_DSP_VS_ST_END_F1, val);
1634 dsp_ctrl |= RK3568_VP_DSP_CTRL__DSP_INTERLACE;
1635 dsp_ctrl |= RK3568_VP_DSP_CTRL__DSP_FILED_POL;
1636 dsp_ctrl |= RK3568_VP_DSP_CTRL__P2I_EN;
1637 vtotal += vtotal + 1;
1638 act_end = vact_end_f1;
1639 } else {
1640 act_end = vact_end;
1641 }
1642
1643 vop2_writel(vop2, RK3568_VP_LINE_FLAG(vp->id),
1644 (act_end - us_to_vertical_line(mode, 0)) << 16 | act_end);
1645
1646 vop2_vp_write(vp, RK3568_VP_DSP_VTOTAL_VS_END, vtotal << 16 | vsync_len);
1647
1648 if (mode->flags & DRM_MODE_FLAG_DBLCLK) {
1649 dsp_ctrl |= RK3568_VP_DSP_CTRL__CORE_DCLK_DIV;
1650 clock *= 2;
1651 }
1652
1653 vop2_vp_write(vp, RK3568_VP_MIPI_CTRL, 0);
1654
1655 clk_set_rate(vp->dclk, clock);
1656
1657 vop2_post_config(crtc);
1658
1659 vop2_cfg_done(vp);
1660
1661 vop2_vp_write(vp, RK3568_VP_DSP_CTRL, dsp_ctrl);
1662
1663 drm_crtc_vblank_on(crtc);
1664
1665 vop2_unlock(vop2);
1666 }
1667
vop2_crtc_atomic_check(struct drm_crtc * crtc,struct drm_atomic_state * state)1668 static int vop2_crtc_atomic_check(struct drm_crtc *crtc,
1669 struct drm_atomic_state *state)
1670 {
1671 struct vop2_video_port *vp = to_vop2_video_port(crtc);
1672 struct drm_plane *plane;
1673 int nplanes = 0;
1674 struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state, crtc);
1675
1676 drm_atomic_crtc_state_for_each_plane(plane, crtc_state)
1677 nplanes++;
1678
1679 if (nplanes > vp->nlayers)
1680 return -EINVAL;
1681
1682 return 0;
1683 }
1684
is_opaque(u16 alpha)1685 static bool is_opaque(u16 alpha)
1686 {
1687 return (alpha >> 8) == 0xff;
1688 }
1689
vop2_parse_alpha(struct vop2_alpha_config * alpha_config,struct vop2_alpha * alpha)1690 static void vop2_parse_alpha(struct vop2_alpha_config *alpha_config,
1691 struct vop2_alpha *alpha)
1692 {
1693 int src_glb_alpha_en = is_opaque(alpha_config->src_glb_alpha_value) ? 0 : 1;
1694 int dst_glb_alpha_en = is_opaque(alpha_config->dst_glb_alpha_value) ? 0 : 1;
1695 int src_color_mode = alpha_config->src_premulti_en ?
1696 ALPHA_SRC_PRE_MUL : ALPHA_SRC_NO_PRE_MUL;
1697 int dst_color_mode = alpha_config->dst_premulti_en ?
1698 ALPHA_SRC_PRE_MUL : ALPHA_SRC_NO_PRE_MUL;
1699
1700 alpha->src_color_ctrl.val = 0;
1701 alpha->dst_color_ctrl.val = 0;
1702 alpha->src_alpha_ctrl.val = 0;
1703 alpha->dst_alpha_ctrl.val = 0;
1704
1705 if (!alpha_config->src_pixel_alpha_en)
1706 alpha->src_color_ctrl.bits.blend_mode = ALPHA_GLOBAL;
1707 else if (alpha_config->src_pixel_alpha_en && !src_glb_alpha_en)
1708 alpha->src_color_ctrl.bits.blend_mode = ALPHA_PER_PIX;
1709 else
1710 alpha->src_color_ctrl.bits.blend_mode = ALPHA_PER_PIX_GLOBAL;
1711
1712 alpha->src_color_ctrl.bits.alpha_en = 1;
1713
1714 if (alpha->src_color_ctrl.bits.blend_mode == ALPHA_GLOBAL) {
1715 alpha->src_color_ctrl.bits.color_mode = src_color_mode;
1716 alpha->src_color_ctrl.bits.factor_mode = SRC_FAC_ALPHA_SRC_GLOBAL;
1717 } else if (alpha->src_color_ctrl.bits.blend_mode == ALPHA_PER_PIX) {
1718 alpha->src_color_ctrl.bits.color_mode = src_color_mode;
1719 alpha->src_color_ctrl.bits.factor_mode = SRC_FAC_ALPHA_ONE;
1720 } else {
1721 alpha->src_color_ctrl.bits.color_mode = ALPHA_SRC_PRE_MUL;
1722 alpha->src_color_ctrl.bits.factor_mode = SRC_FAC_ALPHA_SRC_GLOBAL;
1723 }
1724 alpha->src_color_ctrl.bits.glb_alpha = alpha_config->src_glb_alpha_value >> 8;
1725 alpha->src_color_ctrl.bits.alpha_mode = ALPHA_STRAIGHT;
1726 alpha->src_color_ctrl.bits.alpha_cal_mode = ALPHA_SATURATION;
1727
1728 alpha->dst_color_ctrl.bits.alpha_mode = ALPHA_STRAIGHT;
1729 alpha->dst_color_ctrl.bits.alpha_cal_mode = ALPHA_SATURATION;
1730 alpha->dst_color_ctrl.bits.blend_mode = ALPHA_GLOBAL;
1731 alpha->dst_color_ctrl.bits.glb_alpha = alpha_config->dst_glb_alpha_value >> 8;
1732 alpha->dst_color_ctrl.bits.color_mode = dst_color_mode;
1733 alpha->dst_color_ctrl.bits.factor_mode = ALPHA_SRC_INVERSE;
1734
1735 alpha->src_alpha_ctrl.bits.alpha_mode = ALPHA_STRAIGHT;
1736 alpha->src_alpha_ctrl.bits.blend_mode = alpha->src_color_ctrl.bits.blend_mode;
1737 alpha->src_alpha_ctrl.bits.alpha_cal_mode = ALPHA_SATURATION;
1738 alpha->src_alpha_ctrl.bits.factor_mode = ALPHA_ONE;
1739
1740 alpha->dst_alpha_ctrl.bits.alpha_mode = ALPHA_STRAIGHT;
1741 if (alpha_config->dst_pixel_alpha_en && !dst_glb_alpha_en)
1742 alpha->dst_alpha_ctrl.bits.blend_mode = ALPHA_PER_PIX;
1743 else
1744 alpha->dst_alpha_ctrl.bits.blend_mode = ALPHA_PER_PIX_GLOBAL;
1745 alpha->dst_alpha_ctrl.bits.alpha_cal_mode = ALPHA_NO_SATURATION;
1746 alpha->dst_alpha_ctrl.bits.factor_mode = ALPHA_SRC_INVERSE;
1747 }
1748
vop2_find_start_mixer_id_for_vp(struct vop2 * vop2,u8 port_id)1749 static int vop2_find_start_mixer_id_for_vp(struct vop2 *vop2, u8 port_id)
1750 {
1751 struct vop2_video_port *vp;
1752 int used_layer = 0;
1753 int i;
1754
1755 for (i = 0; i < port_id; i++) {
1756 vp = &vop2->vps[i];
1757 used_layer += hweight32(vp->win_mask);
1758 }
1759
1760 return used_layer;
1761 }
1762
vop2_setup_cluster_alpha(struct vop2 * vop2,struct vop2_win * main_win)1763 static void vop2_setup_cluster_alpha(struct vop2 *vop2, struct vop2_win *main_win)
1764 {
1765 struct vop2_alpha_config alpha_config;
1766 struct vop2_alpha alpha;
1767 struct drm_plane_state *bottom_win_pstate;
1768 bool src_pixel_alpha_en = false;
1769 u16 src_glb_alpha_val, dst_glb_alpha_val;
1770 bool premulti_en = false;
1771 bool swap = false;
1772 u32 offset = 0;
1773
1774 /* At one win mode, win0 is dst/bottom win, and win1 is a all zero src/top win */
1775 bottom_win_pstate = main_win->base.state;
1776 src_glb_alpha_val = 0;
1777 dst_glb_alpha_val = main_win->base.state->alpha;
1778
1779 if (!bottom_win_pstate->fb)
1780 return;
1781
1782 alpha_config.src_premulti_en = premulti_en;
1783 alpha_config.dst_premulti_en = false;
1784 alpha_config.src_pixel_alpha_en = src_pixel_alpha_en;
1785 alpha_config.dst_pixel_alpha_en = true; /* alpha value need transfer to next mix */
1786 alpha_config.src_glb_alpha_value = src_glb_alpha_val;
1787 alpha_config.dst_glb_alpha_value = dst_glb_alpha_val;
1788 vop2_parse_alpha(&alpha_config, &alpha);
1789
1790 alpha.src_color_ctrl.bits.src_dst_swap = swap;
1791
1792 switch (main_win->data->phys_id) {
1793 case ROCKCHIP_VOP2_CLUSTER0:
1794 offset = 0x0;
1795 break;
1796 case ROCKCHIP_VOP2_CLUSTER1:
1797 offset = 0x10;
1798 break;
1799 case ROCKCHIP_VOP2_CLUSTER2:
1800 offset = 0x20;
1801 break;
1802 case ROCKCHIP_VOP2_CLUSTER3:
1803 offset = 0x30;
1804 break;
1805 }
1806
1807 vop2_writel(vop2, RK3568_CLUSTER0_MIX_SRC_COLOR_CTRL + offset,
1808 alpha.src_color_ctrl.val);
1809 vop2_writel(vop2, RK3568_CLUSTER0_MIX_DST_COLOR_CTRL + offset,
1810 alpha.dst_color_ctrl.val);
1811 vop2_writel(vop2, RK3568_CLUSTER0_MIX_SRC_ALPHA_CTRL + offset,
1812 alpha.src_alpha_ctrl.val);
1813 vop2_writel(vop2, RK3568_CLUSTER0_MIX_DST_ALPHA_CTRL + offset,
1814 alpha.dst_alpha_ctrl.val);
1815 }
1816
vop2_setup_alpha(struct vop2_video_port * vp)1817 static void vop2_setup_alpha(struct vop2_video_port *vp)
1818 {
1819 struct vop2 *vop2 = vp->vop2;
1820 struct drm_framebuffer *fb;
1821 struct vop2_alpha_config alpha_config;
1822 struct vop2_alpha alpha;
1823 struct drm_plane *plane;
1824 int pixel_alpha_en;
1825 int premulti_en, gpremulti_en = 0;
1826 int mixer_id;
1827 u32 offset;
1828 bool bottom_layer_alpha_en = false;
1829 u32 dst_global_alpha = DRM_BLEND_ALPHA_OPAQUE;
1830
1831 mixer_id = vop2_find_start_mixer_id_for_vp(vop2, vp->id);
1832 alpha_config.dst_pixel_alpha_en = true; /* alpha value need transfer to next mix */
1833
1834 drm_atomic_crtc_for_each_plane(plane, &vp->crtc) {
1835 struct vop2_win *win = to_vop2_win(plane);
1836
1837 if (plane->state->normalized_zpos == 0 &&
1838 !is_opaque(plane->state->alpha) &&
1839 !vop2_cluster_window(win)) {
1840 /*
1841 * If bottom layer have global alpha effect [except cluster layer,
1842 * because cluster have deal with bottom layer global alpha value
1843 * at cluster mix], bottom layer mix need deal with global alpha.
1844 */
1845 bottom_layer_alpha_en = true;
1846 dst_global_alpha = plane->state->alpha;
1847 }
1848 }
1849
1850 drm_atomic_crtc_for_each_plane(plane, &vp->crtc) {
1851 struct vop2_win *win = to_vop2_win(plane);
1852 int zpos = plane->state->normalized_zpos;
1853
1854 /*
1855 * Need to configure alpha from second layer.
1856 */
1857 if (zpos == 0)
1858 continue;
1859
1860 if (plane->state->pixel_blend_mode == DRM_MODE_BLEND_PREMULTI)
1861 premulti_en = 1;
1862 else
1863 premulti_en = 0;
1864
1865 plane = &win->base;
1866 fb = plane->state->fb;
1867
1868 pixel_alpha_en = fb->format->has_alpha;
1869
1870 alpha_config.src_premulti_en = premulti_en;
1871
1872 if (bottom_layer_alpha_en && zpos == 1) {
1873 gpremulti_en = premulti_en;
1874 /* Cd = Cs + (1 - As) * Cd * Agd */
1875 alpha_config.dst_premulti_en = false;
1876 alpha_config.src_pixel_alpha_en = pixel_alpha_en;
1877 alpha_config.src_glb_alpha_value = plane->state->alpha;
1878 alpha_config.dst_glb_alpha_value = dst_global_alpha;
1879 } else if (vop2_cluster_window(win)) {
1880 /* Mix output data only have pixel alpha */
1881 alpha_config.dst_premulti_en = true;
1882 alpha_config.src_pixel_alpha_en = true;
1883 alpha_config.src_glb_alpha_value = DRM_BLEND_ALPHA_OPAQUE;
1884 alpha_config.dst_glb_alpha_value = DRM_BLEND_ALPHA_OPAQUE;
1885 } else {
1886 /* Cd = Cs + (1 - As) * Cd */
1887 alpha_config.dst_premulti_en = true;
1888 alpha_config.src_pixel_alpha_en = pixel_alpha_en;
1889 alpha_config.src_glb_alpha_value = plane->state->alpha;
1890 alpha_config.dst_glb_alpha_value = DRM_BLEND_ALPHA_OPAQUE;
1891 }
1892
1893 vop2_parse_alpha(&alpha_config, &alpha);
1894
1895 offset = (mixer_id + zpos - 1) * 0x10;
1896 vop2_writel(vop2, RK3568_MIX0_SRC_COLOR_CTRL + offset,
1897 alpha.src_color_ctrl.val);
1898 vop2_writel(vop2, RK3568_MIX0_DST_COLOR_CTRL + offset,
1899 alpha.dst_color_ctrl.val);
1900 vop2_writel(vop2, RK3568_MIX0_SRC_ALPHA_CTRL + offset,
1901 alpha.src_alpha_ctrl.val);
1902 vop2_writel(vop2, RK3568_MIX0_DST_ALPHA_CTRL + offset,
1903 alpha.dst_alpha_ctrl.val);
1904 }
1905
1906 if (vp->id == 0) {
1907 if (bottom_layer_alpha_en) {
1908 /* Transfer pixel alpha to hdr mix */
1909 alpha_config.src_premulti_en = gpremulti_en;
1910 alpha_config.dst_premulti_en = true;
1911 alpha_config.src_pixel_alpha_en = true;
1912 alpha_config.src_glb_alpha_value = DRM_BLEND_ALPHA_OPAQUE;
1913 alpha_config.dst_glb_alpha_value = DRM_BLEND_ALPHA_OPAQUE;
1914 vop2_parse_alpha(&alpha_config, &alpha);
1915
1916 vop2_writel(vop2, RK3568_HDR0_SRC_COLOR_CTRL,
1917 alpha.src_color_ctrl.val);
1918 vop2_writel(vop2, RK3568_HDR0_DST_COLOR_CTRL,
1919 alpha.dst_color_ctrl.val);
1920 vop2_writel(vop2, RK3568_HDR0_SRC_ALPHA_CTRL,
1921 alpha.src_alpha_ctrl.val);
1922 vop2_writel(vop2, RK3568_HDR0_DST_ALPHA_CTRL,
1923 alpha.dst_alpha_ctrl.val);
1924 } else {
1925 vop2_writel(vop2, RK3568_HDR0_SRC_COLOR_CTRL, 0);
1926 }
1927 }
1928 }
1929
vop2_setup_layer_mixer(struct vop2_video_port * vp)1930 static void vop2_setup_layer_mixer(struct vop2_video_port *vp)
1931 {
1932 struct vop2 *vop2 = vp->vop2;
1933 struct drm_plane *plane;
1934 u32 layer_sel = 0;
1935 u32 port_sel;
1936 u8 layer_id;
1937 u8 old_layer_id;
1938 u8 layer_sel_id;
1939 unsigned int ofs;
1940 u32 ovl_ctrl;
1941 int i;
1942 struct vop2_video_port *vp0 = &vop2->vps[0];
1943 struct vop2_video_port *vp1 = &vop2->vps[1];
1944 struct vop2_video_port *vp2 = &vop2->vps[2];
1945 struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(vp->crtc.state);
1946
1947 ovl_ctrl = vop2_readl(vop2, RK3568_OVL_CTRL);
1948 ovl_ctrl |= RK3568_OVL_CTRL__LAYERSEL_REGDONE_IMD;
1949 if (vcstate->yuv_overlay)
1950 ovl_ctrl |= RK3568_OVL_CTRL__YUV_MODE(vp->id);
1951 else
1952 ovl_ctrl &= ~RK3568_OVL_CTRL__YUV_MODE(vp->id);
1953
1954 vop2_writel(vop2, RK3568_OVL_CTRL, ovl_ctrl);
1955
1956 port_sel = vop2_readl(vop2, RK3568_OVL_PORT_SEL);
1957 port_sel &= RK3568_OVL_PORT_SEL__SEL_PORT;
1958
1959 if (vp0->nlayers)
1960 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SET__PORT0_MUX,
1961 vp0->nlayers - 1);
1962 else
1963 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SET__PORT0_MUX, 8);
1964
1965 if (vp1->nlayers)
1966 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SET__PORT1_MUX,
1967 (vp0->nlayers + vp1->nlayers - 1));
1968 else
1969 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SET__PORT1_MUX, 8);
1970
1971 if (vp2->nlayers)
1972 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SET__PORT2_MUX,
1973 (vp2->nlayers + vp1->nlayers + vp0->nlayers - 1));
1974 else
1975 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SET__PORT2_MUX, 8);
1976
1977 layer_sel = vop2_readl(vop2, RK3568_OVL_LAYER_SEL);
1978
1979 ofs = 0;
1980 for (i = 0; i < vp->id; i++)
1981 ofs += vop2->vps[i].nlayers;
1982
1983 drm_atomic_crtc_for_each_plane(plane, &vp->crtc) {
1984 struct vop2_win *win = to_vop2_win(plane);
1985 struct vop2_win *old_win;
1986
1987 layer_id = (u8)(plane->state->normalized_zpos + ofs);
1988
1989 /*
1990 * Find the layer this win bind in old state.
1991 */
1992 for (old_layer_id = 0; old_layer_id < vop2->data->win_size; old_layer_id++) {
1993 layer_sel_id = (layer_sel >> (4 * old_layer_id)) & 0xf;
1994 if (layer_sel_id == win->data->layer_sel_id)
1995 break;
1996 }
1997
1998 /*
1999 * Find the win bind to this layer in old state
2000 */
2001 for (i = 0; i < vop2->data->win_size; i++) {
2002 old_win = &vop2->win[i];
2003 layer_sel_id = (layer_sel >> (4 * layer_id)) & 0xf;
2004 if (layer_sel_id == old_win->data->layer_sel_id)
2005 break;
2006 }
2007
2008 switch (win->data->phys_id) {
2009 case ROCKCHIP_VOP2_CLUSTER0:
2010 port_sel &= ~RK3568_OVL_PORT_SEL__CLUSTER0;
2011 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__CLUSTER0, vp->id);
2012 break;
2013 case ROCKCHIP_VOP2_CLUSTER1:
2014 port_sel &= ~RK3568_OVL_PORT_SEL__CLUSTER1;
2015 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__CLUSTER1, vp->id);
2016 break;
2017 case ROCKCHIP_VOP2_ESMART0:
2018 port_sel &= ~RK3568_OVL_PORT_SEL__ESMART0;
2019 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__ESMART0, vp->id);
2020 break;
2021 case ROCKCHIP_VOP2_ESMART1:
2022 port_sel &= ~RK3568_OVL_PORT_SEL__ESMART1;
2023 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__ESMART1, vp->id);
2024 break;
2025 case ROCKCHIP_VOP2_SMART0:
2026 port_sel &= ~RK3568_OVL_PORT_SEL__SMART0;
2027 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__SMART0, vp->id);
2028 break;
2029 case ROCKCHIP_VOP2_SMART1:
2030 port_sel &= ~RK3568_OVL_PORT_SEL__SMART1;
2031 port_sel |= FIELD_PREP(RK3568_OVL_PORT_SEL__SMART1, vp->id);
2032 break;
2033 }
2034
2035 layer_sel &= ~RK3568_OVL_LAYER_SEL__LAYER(layer_id, 0x7);
2036 layer_sel |= RK3568_OVL_LAYER_SEL__LAYER(layer_id, win->data->layer_sel_id);
2037 /*
2038 * When we bind a window from layerM to layerN, we also need to move the old
2039 * window on layerN to layerM to avoid one window selected by two or more layers.
2040 */
2041 layer_sel &= ~RK3568_OVL_LAYER_SEL__LAYER(old_layer_id, 0x7);
2042 layer_sel |= RK3568_OVL_LAYER_SEL__LAYER(old_layer_id, old_win->data->layer_sel_id);
2043 }
2044
2045 vop2_writel(vop2, RK3568_OVL_LAYER_SEL, layer_sel);
2046 vop2_writel(vop2, RK3568_OVL_PORT_SEL, port_sel);
2047 }
2048
vop2_setup_dly_for_windows(struct vop2 * vop2)2049 static void vop2_setup_dly_for_windows(struct vop2 *vop2)
2050 {
2051 struct vop2_win *win;
2052 int i = 0;
2053 u32 cdly = 0, sdly = 0;
2054
2055 for (i = 0; i < vop2->data->win_size; i++) {
2056 u32 dly;
2057
2058 win = &vop2->win[i];
2059 dly = win->delay;
2060
2061 switch (win->data->phys_id) {
2062 case ROCKCHIP_VOP2_CLUSTER0:
2063 cdly |= FIELD_PREP(RK3568_CLUSTER_DLY_NUM__CLUSTER0_0, dly);
2064 cdly |= FIELD_PREP(RK3568_CLUSTER_DLY_NUM__CLUSTER0_1, dly);
2065 break;
2066 case ROCKCHIP_VOP2_CLUSTER1:
2067 cdly |= FIELD_PREP(RK3568_CLUSTER_DLY_NUM__CLUSTER1_0, dly);
2068 cdly |= FIELD_PREP(RK3568_CLUSTER_DLY_NUM__CLUSTER1_1, dly);
2069 break;
2070 case ROCKCHIP_VOP2_ESMART0:
2071 sdly |= FIELD_PREP(RK3568_SMART_DLY_NUM__ESMART0, dly);
2072 break;
2073 case ROCKCHIP_VOP2_ESMART1:
2074 sdly |= FIELD_PREP(RK3568_SMART_DLY_NUM__ESMART1, dly);
2075 break;
2076 case ROCKCHIP_VOP2_SMART0:
2077 sdly |= FIELD_PREP(RK3568_SMART_DLY_NUM__SMART0, dly);
2078 break;
2079 case ROCKCHIP_VOP2_SMART1:
2080 sdly |= FIELD_PREP(RK3568_SMART_DLY_NUM__SMART1, dly);
2081 break;
2082 }
2083 }
2084
2085 vop2_writel(vop2, RK3568_CLUSTER_DLY_NUM, cdly);
2086 vop2_writel(vop2, RK3568_SMART_DLY_NUM, sdly);
2087 }
2088
vop2_crtc_atomic_begin(struct drm_crtc * crtc,struct drm_atomic_state * state)2089 static void vop2_crtc_atomic_begin(struct drm_crtc *crtc,
2090 struct drm_atomic_state *state)
2091 {
2092 struct vop2_video_port *vp = to_vop2_video_port(crtc);
2093 struct vop2 *vop2 = vp->vop2;
2094 struct drm_plane *plane;
2095
2096 vp->win_mask = 0;
2097
2098 drm_atomic_crtc_for_each_plane(plane, crtc) {
2099 struct vop2_win *win = to_vop2_win(plane);
2100
2101 win->delay = win->data->dly[VOP2_DLY_MODE_DEFAULT];
2102
2103 vp->win_mask |= BIT(win->data->phys_id);
2104
2105 if (vop2_cluster_window(win))
2106 vop2_setup_cluster_alpha(vop2, win);
2107 }
2108
2109 if (!vp->win_mask)
2110 return;
2111
2112 vop2_setup_layer_mixer(vp);
2113 vop2_setup_alpha(vp);
2114 vop2_setup_dly_for_windows(vop2);
2115 }
2116
vop2_crtc_atomic_flush(struct drm_crtc * crtc,struct drm_atomic_state * state)2117 static void vop2_crtc_atomic_flush(struct drm_crtc *crtc,
2118 struct drm_atomic_state *state)
2119 {
2120 struct vop2_video_port *vp = to_vop2_video_port(crtc);
2121
2122 vop2_post_config(crtc);
2123
2124 vop2_cfg_done(vp);
2125
2126 spin_lock_irq(&crtc->dev->event_lock);
2127
2128 if (crtc->state->event) {
2129 WARN_ON(drm_crtc_vblank_get(crtc));
2130 vp->event = crtc->state->event;
2131 crtc->state->event = NULL;
2132 }
2133
2134 spin_unlock_irq(&crtc->dev->event_lock);
2135 }
2136
2137 static const struct drm_crtc_helper_funcs vop2_crtc_helper_funcs = {
2138 .mode_fixup = vop2_crtc_mode_fixup,
2139 .atomic_check = vop2_crtc_atomic_check,
2140 .atomic_begin = vop2_crtc_atomic_begin,
2141 .atomic_flush = vop2_crtc_atomic_flush,
2142 .atomic_enable = vop2_crtc_atomic_enable,
2143 .atomic_disable = vop2_crtc_atomic_disable,
2144 };
2145
vop2_crtc_duplicate_state(struct drm_crtc * crtc)2146 static struct drm_crtc_state *vop2_crtc_duplicate_state(struct drm_crtc *crtc)
2147 {
2148 struct rockchip_crtc_state *vcstate;
2149
2150 if (WARN_ON(!crtc->state))
2151 return NULL;
2152
2153 vcstate = kmemdup(to_rockchip_crtc_state(crtc->state),
2154 sizeof(*vcstate), GFP_KERNEL);
2155 if (!vcstate)
2156 return NULL;
2157
2158 __drm_atomic_helper_crtc_duplicate_state(crtc, &vcstate->base);
2159
2160 return &vcstate->base;
2161 }
2162
vop2_crtc_destroy_state(struct drm_crtc * crtc,struct drm_crtc_state * state)2163 static void vop2_crtc_destroy_state(struct drm_crtc *crtc,
2164 struct drm_crtc_state *state)
2165 {
2166 struct rockchip_crtc_state *vcstate = to_rockchip_crtc_state(state);
2167
2168 __drm_atomic_helper_crtc_destroy_state(&vcstate->base);
2169 kfree(vcstate);
2170 }
2171
vop2_crtc_reset(struct drm_crtc * crtc)2172 static void vop2_crtc_reset(struct drm_crtc *crtc)
2173 {
2174 struct rockchip_crtc_state *vcstate =
2175 kzalloc(sizeof(*vcstate), GFP_KERNEL);
2176
2177 if (crtc->state)
2178 vop2_crtc_destroy_state(crtc, crtc->state);
2179
2180 if (vcstate)
2181 __drm_atomic_helper_crtc_reset(crtc, &vcstate->base);
2182 else
2183 __drm_atomic_helper_crtc_reset(crtc, NULL);
2184 }
2185
2186 static const struct drm_crtc_funcs vop2_crtc_funcs = {
2187 .set_config = drm_atomic_helper_set_config,
2188 .page_flip = drm_atomic_helper_page_flip,
2189 .destroy = drm_crtc_cleanup,
2190 .reset = vop2_crtc_reset,
2191 .atomic_duplicate_state = vop2_crtc_duplicate_state,
2192 .atomic_destroy_state = vop2_crtc_destroy_state,
2193 .enable_vblank = vop2_crtc_enable_vblank,
2194 .disable_vblank = vop2_crtc_disable_vblank,
2195 };
2196
vop2_isr(int irq,void * data)2197 static irqreturn_t vop2_isr(int irq, void *data)
2198 {
2199 struct vop2 *vop2 = data;
2200 const struct vop2_data *vop2_data = vop2->data;
2201 u32 axi_irqs[VOP2_SYS_AXI_BUS_NUM];
2202 int ret = IRQ_NONE;
2203 int i;
2204
2205 /*
2206 * The irq is shared with the iommu. If the runtime-pm state of the
2207 * vop2-device is disabled the irq has to be targeted at the iommu.
2208 */
2209 if (!pm_runtime_get_if_in_use(vop2->dev))
2210 return IRQ_NONE;
2211
2212 for (i = 0; i < vop2_data->nr_vps; i++) {
2213 struct vop2_video_port *vp = &vop2->vps[i];
2214 struct drm_crtc *crtc = &vp->crtc;
2215 u32 irqs;
2216
2217 irqs = vop2_readl(vop2, RK3568_VP_INT_STATUS(vp->id));
2218 vop2_writel(vop2, RK3568_VP_INT_CLR(vp->id), irqs << 16 | irqs);
2219
2220 if (irqs & VP_INT_DSP_HOLD_VALID) {
2221 complete(&vp->dsp_hold_completion);
2222 ret = IRQ_HANDLED;
2223 }
2224
2225 if (irqs & VP_INT_FS_FIELD) {
2226 drm_crtc_handle_vblank(crtc);
2227 spin_lock(&crtc->dev->event_lock);
2228 if (vp->event) {
2229 u32 val = vop2_readl(vop2, RK3568_REG_CFG_DONE);
2230
2231 if (!(val & BIT(vp->id))) {
2232 drm_crtc_send_vblank_event(crtc, vp->event);
2233 vp->event = NULL;
2234 drm_crtc_vblank_put(crtc);
2235 }
2236 }
2237 spin_unlock(&crtc->dev->event_lock);
2238
2239 ret = IRQ_HANDLED;
2240 }
2241
2242 if (irqs & VP_INT_POST_BUF_EMPTY) {
2243 drm_err_ratelimited(vop2->drm,
2244 "POST_BUF_EMPTY irq err at vp%d\n",
2245 vp->id);
2246 ret = IRQ_HANDLED;
2247 }
2248 }
2249
2250 axi_irqs[0] = vop2_readl(vop2, RK3568_SYS0_INT_STATUS);
2251 vop2_writel(vop2, RK3568_SYS0_INT_CLR, axi_irqs[0] << 16 | axi_irqs[0]);
2252 axi_irqs[1] = vop2_readl(vop2, RK3568_SYS1_INT_STATUS);
2253 vop2_writel(vop2, RK3568_SYS1_INT_CLR, axi_irqs[1] << 16 | axi_irqs[1]);
2254
2255 for (i = 0; i < ARRAY_SIZE(axi_irqs); i++) {
2256 if (axi_irqs[i] & VOP2_INT_BUS_ERRPR) {
2257 drm_err_ratelimited(vop2->drm, "BUS_ERROR irq err\n");
2258 ret = IRQ_HANDLED;
2259 }
2260 }
2261
2262 pm_runtime_put(vop2->dev);
2263
2264 return ret;
2265 }
2266
vop2_plane_init(struct vop2 * vop2,struct vop2_win * win,unsigned long possible_crtcs)2267 static int vop2_plane_init(struct vop2 *vop2, struct vop2_win *win,
2268 unsigned long possible_crtcs)
2269 {
2270 const struct vop2_win_data *win_data = win->data;
2271 unsigned int blend_caps = BIT(DRM_MODE_BLEND_PIXEL_NONE) |
2272 BIT(DRM_MODE_BLEND_PREMULTI) |
2273 BIT(DRM_MODE_BLEND_COVERAGE);
2274 int ret;
2275
2276 ret = drm_universal_plane_init(vop2->drm, &win->base, possible_crtcs,
2277 &vop2_plane_funcs, win_data->formats,
2278 win_data->nformats,
2279 win_data->format_modifiers,
2280 win->type, win_data->name);
2281 if (ret) {
2282 drm_err(vop2->drm, "failed to initialize plane %d\n", ret);
2283 return ret;
2284 }
2285
2286 drm_plane_helper_add(&win->base, &vop2_plane_helper_funcs);
2287
2288 if (win->data->supported_rotations)
2289 drm_plane_create_rotation_property(&win->base, DRM_MODE_ROTATE_0,
2290 DRM_MODE_ROTATE_0 |
2291 win->data->supported_rotations);
2292 drm_plane_create_alpha_property(&win->base);
2293 drm_plane_create_blend_mode_property(&win->base, blend_caps);
2294 drm_plane_create_zpos_property(&win->base, win->win_id, 0,
2295 vop2->registered_num_wins - 1);
2296
2297 return 0;
2298 }
2299
find_vp_without_primary(struct vop2 * vop2)2300 static struct vop2_video_port *find_vp_without_primary(struct vop2 *vop2)
2301 {
2302 int i;
2303
2304 for (i = 0; i < vop2->data->nr_vps; i++) {
2305 struct vop2_video_port *vp = &vop2->vps[i];
2306
2307 if (!vp->crtc.port)
2308 continue;
2309 if (vp->primary_plane)
2310 continue;
2311
2312 return vp;
2313 }
2314
2315 return NULL;
2316 }
2317
2318 #define NR_LAYERS 6
2319
vop2_create_crtcs(struct vop2 * vop2)2320 static int vop2_create_crtcs(struct vop2 *vop2)
2321 {
2322 const struct vop2_data *vop2_data = vop2->data;
2323 struct drm_device *drm = vop2->drm;
2324 struct device *dev = vop2->dev;
2325 struct drm_plane *plane;
2326 struct device_node *port;
2327 struct vop2_video_port *vp;
2328 int i, nvp, nvps = 0;
2329 int ret;
2330
2331 for (i = 0; i < vop2_data->nr_vps; i++) {
2332 const struct vop2_video_port_data *vp_data;
2333 struct device_node *np;
2334 char dclk_name[9];
2335
2336 vp_data = &vop2_data->vp[i];
2337 vp = &vop2->vps[i];
2338 vp->vop2 = vop2;
2339 vp->id = vp_data->id;
2340 vp->regs = vp_data->regs;
2341 vp->data = vp_data;
2342
2343 snprintf(dclk_name, sizeof(dclk_name), "dclk_vp%d", vp->id);
2344 vp->dclk = devm_clk_get(vop2->dev, dclk_name);
2345 if (IS_ERR(vp->dclk)) {
2346 drm_err(vop2->drm, "failed to get %s\n", dclk_name);
2347 return PTR_ERR(vp->dclk);
2348 }
2349
2350 np = of_graph_get_remote_node(dev->of_node, i, -1);
2351 if (!np) {
2352 drm_dbg(vop2->drm, "%s: No remote for vp%d\n", __func__, i);
2353 continue;
2354 }
2355 of_node_put(np);
2356
2357 port = of_graph_get_port_by_id(dev->of_node, i);
2358 if (!port) {
2359 drm_err(vop2->drm, "no port node found for video_port%d\n", i);
2360 return -ENOENT;
2361 }
2362
2363 vp->crtc.port = port;
2364 nvps++;
2365 }
2366
2367 nvp = 0;
2368 for (i = 0; i < vop2->registered_num_wins; i++) {
2369 struct vop2_win *win = &vop2->win[i];
2370 u32 possible_crtcs = 0;
2371
2372 if (vop2->data->soc_id == 3566) {
2373 /*
2374 * On RK3566 these windows don't have an independent
2375 * framebuffer. They share the framebuffer with smart0,
2376 * esmart0 and cluster0 respectively.
2377 */
2378 switch (win->data->phys_id) {
2379 case ROCKCHIP_VOP2_SMART1:
2380 case ROCKCHIP_VOP2_ESMART1:
2381 case ROCKCHIP_VOP2_CLUSTER1:
2382 continue;
2383 }
2384 }
2385
2386 if (win->type == DRM_PLANE_TYPE_PRIMARY) {
2387 vp = find_vp_without_primary(vop2);
2388 if (vp) {
2389 possible_crtcs = BIT(nvp);
2390 vp->primary_plane = win;
2391 nvp++;
2392 } else {
2393 /* change the unused primary window to overlay window */
2394 win->type = DRM_PLANE_TYPE_OVERLAY;
2395 }
2396 }
2397
2398 if (win->type == DRM_PLANE_TYPE_OVERLAY)
2399 possible_crtcs = (1 << nvps) - 1;
2400
2401 ret = vop2_plane_init(vop2, win, possible_crtcs);
2402 if (ret) {
2403 drm_err(vop2->drm, "failed to init plane %s: %d\n",
2404 win->data->name, ret);
2405 return ret;
2406 }
2407 }
2408
2409 for (i = 0; i < vop2_data->nr_vps; i++) {
2410 vp = &vop2->vps[i];
2411
2412 if (!vp->crtc.port)
2413 continue;
2414
2415 plane = &vp->primary_plane->base;
2416
2417 ret = drm_crtc_init_with_planes(drm, &vp->crtc, plane, NULL,
2418 &vop2_crtc_funcs,
2419 "video_port%d", vp->id);
2420 if (ret) {
2421 drm_err(vop2->drm, "crtc init for video_port%d failed\n", i);
2422 return ret;
2423 }
2424
2425 drm_crtc_helper_add(&vp->crtc, &vop2_crtc_helper_funcs);
2426
2427 init_completion(&vp->dsp_hold_completion);
2428 }
2429
2430 /*
2431 * On the VOP2 it's very hard to change the number of layers on a VP
2432 * during runtime, so we distribute the layers equally over the used
2433 * VPs
2434 */
2435 for (i = 0; i < vop2->data->nr_vps; i++) {
2436 struct vop2_video_port *vp = &vop2->vps[i];
2437
2438 if (vp->crtc.port)
2439 vp->nlayers = NR_LAYERS / nvps;
2440 }
2441
2442 return 0;
2443 }
2444
vop2_destroy_crtcs(struct vop2 * vop2)2445 static void vop2_destroy_crtcs(struct vop2 *vop2)
2446 {
2447 struct drm_device *drm = vop2->drm;
2448 struct list_head *crtc_list = &drm->mode_config.crtc_list;
2449 struct list_head *plane_list = &drm->mode_config.plane_list;
2450 struct drm_crtc *crtc, *tmpc;
2451 struct drm_plane *plane, *tmpp;
2452
2453 list_for_each_entry_safe(plane, tmpp, plane_list, head)
2454 drm_plane_cleanup(plane);
2455
2456 /*
2457 * Destroy CRTC after vop2_plane_destroy() since vop2_disable_plane()
2458 * references the CRTC.
2459 */
2460 list_for_each_entry_safe(crtc, tmpc, crtc_list, head) {
2461 of_node_put(crtc->port);
2462 drm_crtc_cleanup(crtc);
2463 }
2464 }
2465
vop2_find_rgb_encoder(struct vop2 * vop2)2466 static int vop2_find_rgb_encoder(struct vop2 *vop2)
2467 {
2468 struct device_node *node = vop2->dev->of_node;
2469 struct device_node *endpoint;
2470 int i;
2471
2472 for (i = 0; i < vop2->data->nr_vps; i++) {
2473 endpoint = of_graph_get_endpoint_by_regs(node, i,
2474 ROCKCHIP_VOP2_EP_RGB0);
2475 if (!endpoint)
2476 continue;
2477
2478 of_node_put(endpoint);
2479 return i;
2480 }
2481
2482 return -ENOENT;
2483 }
2484
2485 static struct reg_field vop2_cluster_regs[VOP2_WIN_MAX_REG] = {
2486 [VOP2_WIN_ENABLE] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 0, 0),
2487 [VOP2_WIN_FORMAT] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 1, 5),
2488 [VOP2_WIN_RB_SWAP] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 14, 14),
2489 [VOP2_WIN_DITHER_UP] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 18, 18),
2490 [VOP2_WIN_ACT_INFO] = REG_FIELD(RK3568_CLUSTER_WIN_ACT_INFO, 0, 31),
2491 [VOP2_WIN_DSP_INFO] = REG_FIELD(RK3568_CLUSTER_WIN_DSP_INFO, 0, 31),
2492 [VOP2_WIN_DSP_ST] = REG_FIELD(RK3568_CLUSTER_WIN_DSP_ST, 0, 31),
2493 [VOP2_WIN_YRGB_MST] = REG_FIELD(RK3568_CLUSTER_WIN_YRGB_MST, 0, 31),
2494 [VOP2_WIN_UV_MST] = REG_FIELD(RK3568_CLUSTER_WIN_CBR_MST, 0, 31),
2495 [VOP2_WIN_YUV_CLIP] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 19, 19),
2496 [VOP2_WIN_YRGB_VIR] = REG_FIELD(RK3568_CLUSTER_WIN_VIR, 0, 15),
2497 [VOP2_WIN_UV_VIR] = REG_FIELD(RK3568_CLUSTER_WIN_VIR, 16, 31),
2498 [VOP2_WIN_Y2R_EN] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 8, 8),
2499 [VOP2_WIN_R2Y_EN] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 9, 9),
2500 [VOP2_WIN_CSC_MODE] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL0, 10, 11),
2501
2502 /* Scale */
2503 [VOP2_WIN_SCALE_YRGB_X] = REG_FIELD(RK3568_CLUSTER_WIN_SCL_FACTOR_YRGB, 0, 15),
2504 [VOP2_WIN_SCALE_YRGB_Y] = REG_FIELD(RK3568_CLUSTER_WIN_SCL_FACTOR_YRGB, 16, 31),
2505 [VOP2_WIN_YRGB_VER_SCL_MODE] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL1, 14, 15),
2506 [VOP2_WIN_YRGB_HOR_SCL_MODE] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL1, 12, 13),
2507 [VOP2_WIN_BIC_COE_SEL] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL1, 2, 3),
2508 [VOP2_WIN_VSD_YRGB_GT2] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL1, 28, 28),
2509 [VOP2_WIN_VSD_YRGB_GT4] = REG_FIELD(RK3568_CLUSTER_WIN_CTRL1, 29, 29),
2510
2511 /* cluster regs */
2512 [VOP2_WIN_AFBC_ENABLE] = REG_FIELD(RK3568_CLUSTER_CTRL, 1, 1),
2513 [VOP2_WIN_CLUSTER_ENABLE] = REG_FIELD(RK3568_CLUSTER_CTRL, 0, 0),
2514 [VOP2_WIN_CLUSTER_LB_MODE] = REG_FIELD(RK3568_CLUSTER_CTRL, 4, 7),
2515
2516 /* afbc regs */
2517 [VOP2_WIN_AFBC_FORMAT] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_CTRL, 2, 6),
2518 [VOP2_WIN_AFBC_RB_SWAP] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_CTRL, 9, 9),
2519 [VOP2_WIN_AFBC_UV_SWAP] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_CTRL, 10, 10),
2520 [VOP2_WIN_AFBC_AUTO_GATING_EN] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_OUTPUT_CTRL, 4, 4),
2521 [VOP2_WIN_AFBC_HALF_BLOCK_EN] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_CTRL, 7, 7),
2522 [VOP2_WIN_AFBC_BLOCK_SPLIT_EN] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_CTRL, 8, 8),
2523 [VOP2_WIN_AFBC_HDR_PTR] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_HDR_PTR, 0, 31),
2524 [VOP2_WIN_AFBC_PIC_SIZE] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_PIC_SIZE, 0, 31),
2525 [VOP2_WIN_AFBC_PIC_VIR_WIDTH] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_VIR_WIDTH, 0, 15),
2526 [VOP2_WIN_AFBC_TILE_NUM] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_VIR_WIDTH, 16, 31),
2527 [VOP2_WIN_AFBC_PIC_OFFSET] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_PIC_OFFSET, 0, 31),
2528 [VOP2_WIN_AFBC_DSP_OFFSET] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_DSP_OFFSET, 0, 31),
2529 [VOP2_WIN_AFBC_TRANSFORM_OFFSET] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_TRANSFORM_OFFSET, 0, 31),
2530 [VOP2_WIN_AFBC_ROTATE_90] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE, 0, 0),
2531 [VOP2_WIN_AFBC_ROTATE_270] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE, 1, 1),
2532 [VOP2_WIN_XMIRROR] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE, 2, 2),
2533 [VOP2_WIN_YMIRROR] = REG_FIELD(RK3568_CLUSTER_WIN_AFBCD_ROTATE_MODE, 3, 3),
2534 [VOP2_WIN_UV_SWAP] = { .reg = 0xffffffff },
2535 [VOP2_WIN_COLOR_KEY] = { .reg = 0xffffffff },
2536 [VOP2_WIN_COLOR_KEY_EN] = { .reg = 0xffffffff },
2537 [VOP2_WIN_SCALE_CBCR_X] = { .reg = 0xffffffff },
2538 [VOP2_WIN_SCALE_CBCR_Y] = { .reg = 0xffffffff },
2539 [VOP2_WIN_YRGB_HSCL_FILTER_MODE] = { .reg = 0xffffffff },
2540 [VOP2_WIN_YRGB_VSCL_FILTER_MODE] = { .reg = 0xffffffff },
2541 [VOP2_WIN_CBCR_VER_SCL_MODE] = { .reg = 0xffffffff },
2542 [VOP2_WIN_CBCR_HSCL_FILTER_MODE] = { .reg = 0xffffffff },
2543 [VOP2_WIN_CBCR_HOR_SCL_MODE] = { .reg = 0xffffffff },
2544 [VOP2_WIN_CBCR_VSCL_FILTER_MODE] = { .reg = 0xffffffff },
2545 [VOP2_WIN_VSD_CBCR_GT2] = { .reg = 0xffffffff },
2546 [VOP2_WIN_VSD_CBCR_GT4] = { .reg = 0xffffffff },
2547 };
2548
vop2_cluster_init(struct vop2_win * win)2549 static int vop2_cluster_init(struct vop2_win *win)
2550 {
2551 struct vop2 *vop2 = win->vop2;
2552 struct reg_field *cluster_regs;
2553 int ret, i;
2554
2555 cluster_regs = kmemdup(vop2_cluster_regs, sizeof(vop2_cluster_regs),
2556 GFP_KERNEL);
2557 if (!cluster_regs)
2558 return -ENOMEM;
2559
2560 for (i = 0; i < ARRAY_SIZE(vop2_cluster_regs); i++)
2561 if (cluster_regs[i].reg != 0xffffffff)
2562 cluster_regs[i].reg += win->offset;
2563
2564 ret = devm_regmap_field_bulk_alloc(vop2->dev, vop2->map, win->reg,
2565 cluster_regs,
2566 ARRAY_SIZE(vop2_cluster_regs));
2567
2568 kfree(cluster_regs);
2569
2570 return ret;
2571 };
2572
2573 static struct reg_field vop2_esmart_regs[VOP2_WIN_MAX_REG] = {
2574 [VOP2_WIN_ENABLE] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 0, 0),
2575 [VOP2_WIN_FORMAT] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 1, 5),
2576 [VOP2_WIN_DITHER_UP] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 12, 12),
2577 [VOP2_WIN_RB_SWAP] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 14, 14),
2578 [VOP2_WIN_UV_SWAP] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 16, 16),
2579 [VOP2_WIN_ACT_INFO] = REG_FIELD(RK3568_SMART_REGION0_ACT_INFO, 0, 31),
2580 [VOP2_WIN_DSP_INFO] = REG_FIELD(RK3568_SMART_REGION0_DSP_INFO, 0, 31),
2581 [VOP2_WIN_DSP_ST] = REG_FIELD(RK3568_SMART_REGION0_DSP_ST, 0, 28),
2582 [VOP2_WIN_YRGB_MST] = REG_FIELD(RK3568_SMART_REGION0_YRGB_MST, 0, 31),
2583 [VOP2_WIN_UV_MST] = REG_FIELD(RK3568_SMART_REGION0_CBR_MST, 0, 31),
2584 [VOP2_WIN_YUV_CLIP] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 17, 17),
2585 [VOP2_WIN_YRGB_VIR] = REG_FIELD(RK3568_SMART_REGION0_VIR, 0, 15),
2586 [VOP2_WIN_UV_VIR] = REG_FIELD(RK3568_SMART_REGION0_VIR, 16, 31),
2587 [VOP2_WIN_Y2R_EN] = REG_FIELD(RK3568_SMART_CTRL0, 0, 0),
2588 [VOP2_WIN_R2Y_EN] = REG_FIELD(RK3568_SMART_CTRL0, 1, 1),
2589 [VOP2_WIN_CSC_MODE] = REG_FIELD(RK3568_SMART_CTRL0, 2, 3),
2590 [VOP2_WIN_YMIRROR] = REG_FIELD(RK3568_SMART_CTRL1, 31, 31),
2591 [VOP2_WIN_COLOR_KEY] = REG_FIELD(RK3568_SMART_COLOR_KEY_CTRL, 0, 29),
2592 [VOP2_WIN_COLOR_KEY_EN] = REG_FIELD(RK3568_SMART_COLOR_KEY_CTRL, 31, 31),
2593
2594 /* Scale */
2595 [VOP2_WIN_SCALE_YRGB_X] = REG_FIELD(RK3568_SMART_REGION0_SCL_FACTOR_YRGB, 0, 15),
2596 [VOP2_WIN_SCALE_YRGB_Y] = REG_FIELD(RK3568_SMART_REGION0_SCL_FACTOR_YRGB, 16, 31),
2597 [VOP2_WIN_SCALE_CBCR_X] = REG_FIELD(RK3568_SMART_REGION0_SCL_FACTOR_CBR, 0, 15),
2598 [VOP2_WIN_SCALE_CBCR_Y] = REG_FIELD(RK3568_SMART_REGION0_SCL_FACTOR_CBR, 16, 31),
2599 [VOP2_WIN_YRGB_HOR_SCL_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 0, 1),
2600 [VOP2_WIN_YRGB_HSCL_FILTER_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 2, 3),
2601 [VOP2_WIN_YRGB_VER_SCL_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 4, 5),
2602 [VOP2_WIN_YRGB_VSCL_FILTER_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 6, 7),
2603 [VOP2_WIN_CBCR_HOR_SCL_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 8, 9),
2604 [VOP2_WIN_CBCR_HSCL_FILTER_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 10, 11),
2605 [VOP2_WIN_CBCR_VER_SCL_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 12, 13),
2606 [VOP2_WIN_CBCR_VSCL_FILTER_MODE] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 14, 15),
2607 [VOP2_WIN_BIC_COE_SEL] = REG_FIELD(RK3568_SMART_REGION0_SCL_CTRL, 16, 17),
2608 [VOP2_WIN_VSD_YRGB_GT2] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 8, 8),
2609 [VOP2_WIN_VSD_YRGB_GT4] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 9, 9),
2610 [VOP2_WIN_VSD_CBCR_GT2] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 10, 10),
2611 [VOP2_WIN_VSD_CBCR_GT4] = REG_FIELD(RK3568_SMART_REGION0_CTRL, 11, 11),
2612 [VOP2_WIN_XMIRROR] = { .reg = 0xffffffff },
2613 [VOP2_WIN_CLUSTER_ENABLE] = { .reg = 0xffffffff },
2614 [VOP2_WIN_AFBC_ENABLE] = { .reg = 0xffffffff },
2615 [VOP2_WIN_CLUSTER_LB_MODE] = { .reg = 0xffffffff },
2616 [VOP2_WIN_AFBC_FORMAT] = { .reg = 0xffffffff },
2617 [VOP2_WIN_AFBC_RB_SWAP] = { .reg = 0xffffffff },
2618 [VOP2_WIN_AFBC_UV_SWAP] = { .reg = 0xffffffff },
2619 [VOP2_WIN_AFBC_AUTO_GATING_EN] = { .reg = 0xffffffff },
2620 [VOP2_WIN_AFBC_BLOCK_SPLIT_EN] = { .reg = 0xffffffff },
2621 [VOP2_WIN_AFBC_PIC_VIR_WIDTH] = { .reg = 0xffffffff },
2622 [VOP2_WIN_AFBC_TILE_NUM] = { .reg = 0xffffffff },
2623 [VOP2_WIN_AFBC_PIC_OFFSET] = { .reg = 0xffffffff },
2624 [VOP2_WIN_AFBC_PIC_SIZE] = { .reg = 0xffffffff },
2625 [VOP2_WIN_AFBC_DSP_OFFSET] = { .reg = 0xffffffff },
2626 [VOP2_WIN_AFBC_TRANSFORM_OFFSET] = { .reg = 0xffffffff },
2627 [VOP2_WIN_AFBC_HDR_PTR] = { .reg = 0xffffffff },
2628 [VOP2_WIN_AFBC_HALF_BLOCK_EN] = { .reg = 0xffffffff },
2629 [VOP2_WIN_AFBC_ROTATE_270] = { .reg = 0xffffffff },
2630 [VOP2_WIN_AFBC_ROTATE_90] = { .reg = 0xffffffff },
2631 };
2632
vop2_esmart_init(struct vop2_win * win)2633 static int vop2_esmart_init(struct vop2_win *win)
2634 {
2635 struct vop2 *vop2 = win->vop2;
2636 struct reg_field *esmart_regs;
2637 int ret, i;
2638
2639 esmart_regs = kmemdup(vop2_esmart_regs, sizeof(vop2_esmart_regs),
2640 GFP_KERNEL);
2641 if (!esmart_regs)
2642 return -ENOMEM;
2643
2644 for (i = 0; i < ARRAY_SIZE(vop2_esmart_regs); i++)
2645 if (esmart_regs[i].reg != 0xffffffff)
2646 esmart_regs[i].reg += win->offset;
2647
2648 ret = devm_regmap_field_bulk_alloc(vop2->dev, vop2->map, win->reg,
2649 esmart_regs,
2650 ARRAY_SIZE(vop2_esmart_regs));
2651
2652 kfree(esmart_regs);
2653
2654 return ret;
2655 };
2656
vop2_win_init(struct vop2 * vop2)2657 static int vop2_win_init(struct vop2 *vop2)
2658 {
2659 const struct vop2_data *vop2_data = vop2->data;
2660 struct vop2_win *win;
2661 int i, ret;
2662
2663 for (i = 0; i < vop2_data->win_size; i++) {
2664 const struct vop2_win_data *win_data = &vop2_data->win[i];
2665
2666 win = &vop2->win[i];
2667 win->data = win_data;
2668 win->type = win_data->type;
2669 win->offset = win_data->base;
2670 win->win_id = i;
2671 win->vop2 = vop2;
2672 if (vop2_cluster_window(win))
2673 ret = vop2_cluster_init(win);
2674 else
2675 ret = vop2_esmart_init(win);
2676 if (ret)
2677 return ret;
2678 }
2679
2680 vop2->registered_num_wins = vop2_data->win_size;
2681
2682 return 0;
2683 }
2684
2685 /*
2686 * The window registers are only updated when config done is written.
2687 * Until that they read back the old value. As we read-modify-write
2688 * these registers mark them as non-volatile. This makes sure we read
2689 * the new values from the regmap register cache.
2690 */
2691 static const struct regmap_range vop2_nonvolatile_range[] = {
2692 regmap_reg_range(0x1000, 0x23ff),
2693 };
2694
2695 static const struct regmap_access_table vop2_volatile_table = {
2696 .no_ranges = vop2_nonvolatile_range,
2697 .n_no_ranges = ARRAY_SIZE(vop2_nonvolatile_range),
2698 };
2699
2700 static const struct regmap_config vop2_regmap_config = {
2701 .reg_bits = 32,
2702 .val_bits = 32,
2703 .reg_stride = 4,
2704 .max_register = 0x3000,
2705 .name = "vop2",
2706 .volatile_table = &vop2_volatile_table,
2707 .cache_type = REGCACHE_RBTREE,
2708 };
2709
vop2_bind(struct device * dev,struct device * master,void * data)2710 static int vop2_bind(struct device *dev, struct device *master, void *data)
2711 {
2712 struct platform_device *pdev = to_platform_device(dev);
2713 const struct vop2_data *vop2_data;
2714 struct drm_device *drm = data;
2715 struct vop2 *vop2;
2716 struct resource *res;
2717 size_t alloc_size;
2718 int ret;
2719
2720 vop2_data = of_device_get_match_data(dev);
2721 if (!vop2_data)
2722 return -ENODEV;
2723
2724 /* Allocate vop2 struct and its vop2_win array */
2725 alloc_size = struct_size(vop2, win, vop2_data->win_size);
2726 vop2 = devm_kzalloc(dev, alloc_size, GFP_KERNEL);
2727 if (!vop2)
2728 return -ENOMEM;
2729
2730 vop2->dev = dev;
2731 vop2->data = vop2_data;
2732 vop2->drm = drm;
2733
2734 dev_set_drvdata(dev, vop2);
2735
2736 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "vop");
2737 if (!res) {
2738 drm_err(vop2->drm, "failed to get vop2 register byname\n");
2739 return -EINVAL;
2740 }
2741
2742 vop2->regs = devm_ioremap_resource(dev, res);
2743 if (IS_ERR(vop2->regs))
2744 return PTR_ERR(vop2->regs);
2745 vop2->len = resource_size(res);
2746
2747 vop2->map = devm_regmap_init_mmio(dev, vop2->regs, &vop2_regmap_config);
2748 if (IS_ERR(vop2->map))
2749 return PTR_ERR(vop2->map);
2750
2751 ret = vop2_win_init(vop2);
2752 if (ret)
2753 return ret;
2754
2755 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "gamma-lut");
2756 if (res) {
2757 vop2->lut_regs = devm_ioremap_resource(dev, res);
2758 if (IS_ERR(vop2->lut_regs))
2759 return PTR_ERR(vop2->lut_regs);
2760 }
2761
2762 vop2->grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,grf");
2763
2764 vop2->hclk = devm_clk_get(vop2->dev, "hclk");
2765 if (IS_ERR(vop2->hclk)) {
2766 drm_err(vop2->drm, "failed to get hclk source\n");
2767 return PTR_ERR(vop2->hclk);
2768 }
2769
2770 vop2->aclk = devm_clk_get(vop2->dev, "aclk");
2771 if (IS_ERR(vop2->aclk)) {
2772 drm_err(vop2->drm, "failed to get aclk source\n");
2773 return PTR_ERR(vop2->aclk);
2774 }
2775
2776 vop2->irq = platform_get_irq(pdev, 0);
2777 if (vop2->irq < 0) {
2778 drm_err(vop2->drm, "cannot find irq for vop2\n");
2779 return vop2->irq;
2780 }
2781
2782 mutex_init(&vop2->vop2_lock);
2783
2784 ret = devm_request_irq(dev, vop2->irq, vop2_isr, IRQF_SHARED, dev_name(dev), vop2);
2785 if (ret)
2786 return ret;
2787
2788 ret = vop2_create_crtcs(vop2);
2789 if (ret)
2790 return ret;
2791
2792 ret = vop2_find_rgb_encoder(vop2);
2793 if (ret >= 0) {
2794 vop2->rgb = rockchip_rgb_init(dev, &vop2->vps[ret].crtc,
2795 vop2->drm, ret);
2796 if (IS_ERR(vop2->rgb)) {
2797 if (PTR_ERR(vop2->rgb) == -EPROBE_DEFER) {
2798 ret = PTR_ERR(vop2->rgb);
2799 goto err_crtcs;
2800 }
2801 vop2->rgb = NULL;
2802 }
2803 }
2804
2805 rockchip_drm_dma_init_device(vop2->drm, vop2->dev);
2806
2807 pm_runtime_enable(&pdev->dev);
2808
2809 return 0;
2810
2811 err_crtcs:
2812 vop2_destroy_crtcs(vop2);
2813
2814 return ret;
2815 }
2816
vop2_unbind(struct device * dev,struct device * master,void * data)2817 static void vop2_unbind(struct device *dev, struct device *master, void *data)
2818 {
2819 struct vop2 *vop2 = dev_get_drvdata(dev);
2820
2821 pm_runtime_disable(dev);
2822
2823 if (vop2->rgb)
2824 rockchip_rgb_fini(vop2->rgb);
2825
2826 vop2_destroy_crtcs(vop2);
2827 }
2828
2829 const struct component_ops vop2_component_ops = {
2830 .bind = vop2_bind,
2831 .unbind = vop2_unbind,
2832 };
2833 EXPORT_SYMBOL_GPL(vop2_component_ops);
2834