| /openbmc/qemu/roms/ |
| H A D | Makefile | 7 pxe-rom-e1000 efi-rom-e1000 : VID := 8086 macro
9 pxe-rom-e1000e efi-rom-e1000e : VID := 8086 macro
11 pxe-rom-eepro100 efi-rom-eepro100 : VID := 8086 macro
13 pxe-rom-ne2k_pci efi-rom-ne2k_pci : VID := 1050 macro
15 pxe-rom-pcnet efi-rom-pcnet : VID := 1022 macro
17 pxe-rom-rtl8139 efi-rom-rtl8139 : VID := 10ec macro
19 pxe-rom-virtio efi-rom-virtio : VID := 1af4 macro
21 pxe-rom-vmxnet3 efi-rom-vmxnet3 : VID := 15ad macro
112 cp ipxe/src/bin/$(VID)$(DID).rom ../pc-bios/pxe-$*.rom
117 $(EDK2_EFIROM) -f "0x$(VID)"
[all...] |
| /openbmc/u-boot/board/freescale/common/ |
| H A D | Kconfig | 25 depends on VID
30 functionality. It is used by common VID driver.
33 depends on VID
38 functionality. It is used by common VID driver.
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| /openbmc/linux/drivers/net/ethernet/mellanox/mlxsw/ |
| H A D | spectrum_acl_flex_keys.c | 14 MLXSW_AFK_ELEMENT_INST_U32(VID, 0x08, 0, 12),
22 MLXSW_AFK_ELEMENT_INST_U32(VID, 0x08, 0, 12),
55 MLXSW_AFK_ELEMENT_INST_U32(VID, 0x00, 0, 12),
144 MLXSW_AFK_ELEMENT_INST_U32(VID, 0x04, 16, 12),
150 MLXSW_AFK_ELEMENT_INST_U32(VID, 0x04, 16, 12),
155 MLXSW_AFK_ELEMENT_INST_U32(VID, 0x04, 16, 12),
323 MLXSW_AFK_ELEMENT_INST_U32(VID, 0x04, 18, 12),
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| /openbmc/linux/Documentation/hwmon/ |
| H A D | mp2856.rst | 30 - Can configured VOUT readout in direct or VID format and allows
31 setting of different formats on rails 1 and 2. For VID the following
46 Device supports VID and direct formats for reading output voltage.
47 The below VID modes are supported: AMD SVI3.
|
| H A D | adm1025.rst | 46 input, or as the a fifth digital entry for the VID reading (bit 4). It's
52 properly, you'll have a wrong +12V reading or a wrong VID reading. The way
59 only in that it has "open-drain VID inputs while the ADM1025 has on-chip
60 100k pull-ups on the VID inputs". It doesn't make any difference for us.
|
| H A D | mp2975.rst | 30 - Can configured VOUT readout in direct or VID format and allows
31 setting of different formats on rails 1 and 2. For VID the following
47 Device supports VID and direct formats for reading output voltage.
48 The below VID modes are supported: VR12, VR13, IMVP9.
|
| H A D | w83627hf.rst | 57 VID reading. However the two chips have the identical 128 pin package. So,
58 it is possible or even likely for a w83627thf to have the VID signals routed
60 the w83627thf driver interprets these as VID. If the VID on your board
62 doesn't help, you may just ignore the bogus VID reading with no harm done.
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| H A D | smsc47m192.rst | 36 as well as CPU voltage VID input.
53 a +12V voltage measurement or a 5 bit CPU VID, but not both.
54 The default setting is to use the pin as 12V input, and use only 4 bit VID.
112 vrm CPU VID standard used for decoding CPU voltage
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| H A D | lm78.rst | 38 the LM78 and LM78-J are exactly identical. The LM79 has one more VID line,
43 seven voltage sensors, VID lines, alarms, and some miscellaneous stuff.
67 The VID lines encode the core voltage value: the voltage level your processor
|
| H A D | asb100.rst | 29 sensors, four temperature sensors, VID lines and alarms. In addition to
42 The VID lines encode the core voltage value: the voltage level your
|
| H A D | adm1026.rst | 98 The datasheet shows an example application with VID signals attached to
99 GPIO lines. Unfortunately, the chip may not be connected to the VID lines
101 get a VID voltage.
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| H A D | it87.rst | 241 The IT8712F and IT8716F additionally feature VID inputs, used to report
242 the Vcore voltage of the processor. The early IT8712F have 5 VID pins,
246 The IT8718F and IT8720F also features VID inputs (up to 8 pins) but the value
249 the driver won't notice and report changes in the VID value. The two
250 upper VID bits share their pins with voltage inputs (in5 and in6) so you
312 The VID lines (IT8712F/IT8716F/IT8718F/IT8720F) encode the core voltage value:
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| H A D | w83793.rst | 44 sets of 6-pin CPU VID input.
104 * VID and VRM
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| H A D | lm93.rst | 40 VID" from the datasheet. It greatly simplifies the interface to allow
46 A "0" configures the VID pins for V(ih) = 2.1V min, V(il) = 0.8V max.
47 A "1" configures the VID pins for V(ih) = 0.8V min, V(il) = 0.4V max.
49 I.e. this parameter controls the VID pin input thresholds; if your VID
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| /openbmc/linux/drivers/gpu/drm/sti/ |
| H A D | NOTES | 11 - The video plug (VID) connects to the HQVDP output.
28 Vid >--+ HQVDP +--+VID Aux +---+ | :===========:
42 buffers) and to HQVDP+VID (video buffers)
56 +-> | HQVDP | |VID Aux |<+ | | | :===========: |
|
| /openbmc/u-boot/doc/ |
| H A D | README.t1040-l2switch | 41 if [vlan <vid>] is missing, VID 1 will be used
45 ethsw [port <port_no>] egress tag { [help] | show | pvid | classified } - configure VID source for …
46 Tag's VID could be the frame's classified VID or the PVID of the port
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| H A D | README.ubispl | 105 * The VID and Data offset depend on the capability of the
108 * If the flash chip supports subpage writes, then the VID
110 * with 4 subpages the VID offset is 512. The DATA offset is 2k.
113 * VID offset is FLASH_PAGE_SIZE and the DATA offset
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| H A D | README.ubi | 13 - Show or set current partition (with optional VID header offset)
57 UBI: VID header offset: 64 (aligned 64)
129 UBI: VID header offset: 64 (aligned 64)
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| /openbmc/linux/Documentation/usb/ |
| H A D | linux-cdc-acm.inf | 82 ; When developing your USB device, the VID and PID used in the PC side
84 ; Modify the below line to use your VID and PID. Use the format as shown
87 ; VID and PIDs. For each supported device, append
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| /openbmc/linux/drivers/cpufreq/ |
| H A D | powernow-k7.h | 12 VID:5, // 12:8 member
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| /openbmc/linux/include/uapi/linux/ |
| H A D | if_vlan.h | 56 int VID; member
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| /openbmc/u-boot/doc/imx/misc/ |
| H A D | sdp.txt | 51 the boot ROM's SDP protocol. The USB VID/PID will depend on standard
53 imx_usb is aware of the USB VID/PID for your device by adding a
82 consecutive reenumerations by adding multiple VID/PID specifications
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| /openbmc/linux/Documentation/networking/ |
| H A D | switchdev.rst | 189 bridge fdb add dev DEV ADDRESS [vlan VID] [self] static
202 bridge fdb add dev DEV ADDRESS [vlan VID] master static
440 of a VLAN-aware bridge doing ingress VID checking). See below for details.
465 device with a VID that is not programmed into the bridge/switch's VLAN table
469 the device with a VID that is not programmed into the bridges/switch's VLAN
470 table must be dropped (strict VID checking).
485 configured to map all traffic, except the packets tagged with a VID
486 belonging to a VLAN upper interface, to an internal VID corresponding to
487 untagged packets. This internal VID spans all ports of the VLAN-unaware
488 bridge. The VID corresponding to the VLAN upper interface spans the
[all …]
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| /openbmc/u-boot/board/freescale/t4qds/ |
| H A D | README | 67 - Regulators can be controlled by VID and/or software
121 T4240 has a VID feature. U-Boot reads the VID efuses and adjust the voltage
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| /openbmc/qemu/include/hw/ppc/ |
| H A D | openpic.h | 10 #define VID 0x03 /* MPIC version ID */ macro
|