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Searched refs:VGT_DEBUG_REG32__tess_topology_p5_q_MASK (Results 1 – 4 of 4) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/gca/
H A Dgfx_6_0_sh_mask.h12064 #define VGT_DEBUG_REG32__tess_topology_p5_q_MASK 0x00003000L macro
H A Dgfx_7_2_sh_mask.h17931 #define VGT_DEBUG_REG32__tess_topology_p5_q_MASK 0x3000 macro
H A Dgfx_8_0_sh_mask.h20189 #define VGT_DEBUG_REG32__tess_topology_p5_q_MASK 0x3000 macro
H A Dgfx_8_1_sh_mask.h20791 #define VGT_DEBUG_REG32__tess_topology_p5_q_MASK 0x3000 macro