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Searched refs:VECS0 (Results 1 – 17 of 17) sorted by relevance

/openbmc/linux/drivers/gpu/drm/i915/
H A Di915_pci.c454 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
506 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1)
569 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
590 BIT(RCS0) | BIT(VCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS1),
623 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
652 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
659 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0),
677 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) |
687 BIT(RCS0) | BIT(BCS0) | BIT(VECS0) | BIT(VCS0) | BIT(VCS2),
748 BIT(VECS0) | BIT(VECS1) | BIT(VECS2) | BIT(VECS3) |
[all …]
H A Di915_drv.h723 ENGINE_INSTANCES_MASK(gt, VECS0, I915_MAX_VECS)
H A Di915_gpu_error.c1307 case VECS0: in engine_record_registers()
/openbmc/linux/drivers/gpu/drm/i915/gvt/
H A Dmmio_context.c135 {VECS0, RING_EXCC(VEBOX_RING_BASE), 0xffff, false}, /* 0x1a028 */
163 [VECS0] = 0xcb00,
350 [VECS0] = 0x4270,
407 [VECS0] = 0xcb00, in switch_mocs()
H A Dexeclist.c53 [VECS0] = VECS_AS_CONTEXT_SWITCH,
H A Dcmd_parser.c430 #define R_VECS BIT(VECS0)
630 [VECS0] = {
1172 [VECS0] = {
H A Dhandlers.c338 engine_mask |= BIT(VECS0); in gdrst_mmio_write()
2093 id = VECS0; in gvt_reg_tlb_control_handler()
/openbmc/linux/drivers/gpu/drm/i915/gt/
H A Dintel_engine_types.h132 VECS0, enumerator
136 #define _VECS(n) (VECS0 + (n))
H A Dintel_engine_user.c170 [VIDEO_ENHANCEMENT_CLASS] = { VECS0, I915_MAX_VECS }, in legacy_ring_idx()
H A Dintel_engine_cs.c193 [VECS0] = {
421 [VECS0] = GEN11_GRDOM_VECS, in get_reset_domain()
440 [VECS0] = GEN6_GRDOM_VECS, in get_reset_domain()
1716 [VECS0] = MSG_IDLE_VECS0, in __cs_pending_mi_force_wakes()
H A Dintel_mocs.c623 [VECS0] = __GEN9_VECS0_MOCS0, in mocs_offset()
H A Dintel_gt_irq.c548 if (HAS_ENGINE(gt, VECS0)) { in gen5_gt_irq_postinstall()
H A Dgen8_engine_cs.c179 case VECS0: in gen12_get_aux_inv_reg()
H A Dintel_ring_submission.c102 case VECS0: in set_hwsp()
H A Dintel_rps.c1933 intel_engine_cs_irq(gt->engine[VECS0], pm_iir >> 10); in gen6_rps_irq_handler()
H A Dintel_execlists_submission.c3506 [VECS0] = GEN8_VECS_IRQ_SHIFT, in logical_ring_default_irqs()
/openbmc/linux/drivers/gpu/drm/i915/gem/
H A Di915_gem_execbuffer.c2483 [I915_EXEC_VEBOX] = VECS0