Home
last modified time | relevance | path

Searched refs:VC7_FOD_1ST_STAGE_RATE_MIN (Results 1 – 1 of 1) sorted by relevance

/openbmc/linux/drivers/clk/
H A Dclk-versaclock7.c59 #define VC7_FOD_1ST_STAGE_RATE_MIN 33000000UL /* 33 MHz */ macro
827 if (first_stage_rate < VC7_FOD_1ST_STAGE_RATE_MIN) { in vc7_calc_fod_divider()
848 first_stage_rate > VC7_FOD_1ST_STAGE_RATE_MIN) { in vc7_calc_fod_divider()
854 first_stage_rate >= VC7_FOD_1ST_STAGE_RATE_MIN && in vc7_calc_fod_divider()