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Searched refs:VC3_PLL2_M_DIVIDER (Results 1 – 1 of 1) sorted by relevance

/openbmc/linux/drivers/clk/
H A Dclk-versaclock3.c49 #define VC3_PLL2_M_DIVIDER 0x1a macro
263 regmap_read(vc3->regmap, VC3_PLL2_M_DIVIDER, &premul); in vc3_pfd_recalc_rate()
658 .offs = VC3_PLL2_M_DIVIDER,