Searched refs:VC3_PLL2_FB_FRC_DIV_MSB (Results 1 – 1 of 1) sorted by relevance
46 #define VC3_PLL2_FB_FRC_DIV_MSB 0x12 macro370 regmap_read(vc3->regmap, VC3_PLL2_FB_FRC_DIV_MSB, &val); in vc3_pll_recalc_rate()428 regmap_write(vc3->regmap, VC3_PLL2_FB_FRC_DIV_MSB, in vc3_pll_set_rate()