Home
last modified time | relevance | path

Searched refs:VC3_MPAR_RL (Results 1 – 1 of 1) sorted by relevance

/openbmc/u-boot/arch/mips/mach-mscc/include/mach/
H A Dddr.h197 #define VC3_MPAR_RL VC3_MPAR_CL macro
199 #define VC3_MPAR_WL (VC3_MPAR_RL - 1)
225 #define MSCC_MEMPARM_MR0 ((VC3_MPAR_RL - 4) << 4) | ((VC3_MPAR_tWR - 4) << 9)
250 ICPU_MEMCTRL_TIMING0_RD_TO_WR_DLY(VC3_MPAR_RL + VC3_MPAR_BL + 1 - \
260 ICPU_MEMCTRL_TIMING0_RD_DATA_XFR_DLY(VC3_MPAR_RL - 3)
283 ICPU_MEMCTRL_TIMING3_LOCAL_ODT_RD_DLY(VC3_MPAR_RL - 3)