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/openbmc/qemu/target/s390x/tcg/
H A Dinsn-format.h.inc57 F3(VRI_a, V(1,8), I(2,16,16), M(3,32))
58 F4(VRI_b, V(1,8), I(2,16,8), I(3,24,8), M(4,32))
59 F4(VRI_c, V(1,8), V(3,12), I(2,16,16), M(4,32))
60 F5(VRI_d, V(1,8), V(2,12), V(3,16), I(4,24,8), M(5,32))
61 F5(VRI_e, V(1,8), V(2,12), I(3,16,12), M(5,28), M(4,32))
62 F5(VRI_f, V(1,8), V(2,12), V(3,16), M(5,24), I(4,28,8))
63 F5(VRI_g, V(1,8), V(2,12), I(4,16,8), M(5,24), I(3,28,8))
64 F3(VRI_h, V(1,8), I(2,16,16), I(3,32,4))
65 F4(VRI_i, V(1,8), R(2,12), M(4,24), I(3,28,8))
66 F5(VRR_a, V(1,8), V(2,12), M(5,24), M(4,28), M(3,32))
[all …]
H A Dinsn-data.h.inc494 C(0xe727, LCBB, RXE, V, la2, 0, new, r1_32, lcbb, 0)
1024 E(0xe713, VGEF, VRV, V, la2, 0, 0, 0, vge, 0, ES_32, IF_VEC)
1025 E(0xe712, VGEG, VRV, V, la2, 0, 0, 0, vge, 0, ES_64, IF_VEC)
1027 F(0xe744, VGBM, VRI_a, V, 0, 0, 0, 0, vgbm, 0, IF_VEC)
1029 F(0xe746, VGM, VRI_b, V, 0, 0, 0, 0, vgm, 0, IF_VEC)
1031 F(0xe706, VL, VRX, V, la2, 0, 0, 0, vl, 0, IF_VEC)
1032 F(0xe756, VLR, VRR_a, V, 0, 0, 0, 0, vlr, 0, IF_VEC)
1034 F(0xe705, VLREP, VRX, V, la2, 0, 0, 0, vlrep, 0, IF_VEC)
1046 E(0xe700, VLEB, VRX, V, la2, 0, 0, 0, vle, 0, ES_8, IF_VEC)
1047 E(0xe701, VLEH, VRX, V, la2, 0, 0, 0, vle, 0, ES_16, IF_VEC)
[all …]
/openbmc/qemu/tests/tcg/i386/
H A Dx86.csv105 # V, I, N.E., N.P., N.S., or N.I.
107 # column is "V" (valid) or not.
110 # with an incorrect "V" in the Valid32 column.
176 "PUSH imm32","-/PUSHL/PUSHQ imm32","-/pushl/pushq imm32","68 id","V","N.S.","","operand32","r","Y",…
177 "PUSH imm32","-/PUSHL/PUSHQ imm32","-/pushl/pushq imm32","68 id","N.S.","V","","default64","r","Y",…
178 "AAA","AAA","aaa","37","V","N.S.","","","","",""
179 "AAD","AAD","aad","D5 0A","V","I","","pseudo","","",""
180 "AAD imm8u","AAD imm8u","aad imm8u","D5 ib","V","N.S.","","","r","",""
181 "AAM","AAM","aam","D4 0A","V","I","","pseudo","","",""
182 "AAM imm8u","AAM imm8u","aam imm8u","D4 ib","V","N.S.","","","r","",""
[all …]
/openbmc/u-boot/arch/arm/dts/
H A Dexynos4412-odroid.dts59 regulator-name = "VDD_ALIVE_1.0V";
65 regulator-name = "VDDQ_VM1M2_1.2V";
77 regulator-name = "VDDQ_MMC2_2.8V";
83 regulator-name = "VDDQ_MMC0/1/3_1.8V";
89 regulator-name = "VMPLL_1.0V";
95 regulator-name = "VPLL_1.1V";
101 regulator-name = "VDD_MIPI/HDMI_1.0V";
107 regulator-name = "VDD_MIPI/HDMI_1.8V";
113 regulator-name = "VDD_ABB1_1.8V";
119 regulator-name = "VDD_UOTG_3.0V";
[all …]
H A Ds5pc1xx-goni.dts51 regulator-name = "VALIVE_1.1V";
59 regulator-name = "VUSB+MIPI_1.1V";
67 regulator-name = "VADC_3.3V";
74 regulator-name = "VTF_2.8V";
81 regulator-name = "VCC_3.3V";
88 regulator-name = "VLCD_1.8V";
96 regulator-name = "VUSB+VDAC_3.3V";
103 regulator-name = "VCC+VCAM_2.8V";
110 regulator-name = "VPLL_1.1V";
118 regulator-name = "CAM_IO_2.8V";
[all …]
H A Dexynos4210-universal_c210.dts82 regulator-name = "VALIVE_1.2V";
89 regulator-name = "VUSB+MIPI_1.1V";
96 regulator-name = "VADC_3.3V";
102 regulator-name = "VTF_2.8V";
114 regulator-name = "VLCD+VMIPI_1.8V";
120 regulator-name = "VUSB+VDAC_3.3V";
127 regulator-name = "VCC_2.8V";
134 regulator-name = "VPLL_1.1V";
142 regulator-name = "CAM_AF_3.3V";
148 regulator-name = "PS_2.8V";
[all …]
H A Dexynos4412-trats2.dts197 regulator-name = "VMIPI_1.0V";
205 regulator-name = "CAM_ISP_MIPI_1.2V";
213 regulator-name = "VMIPI_1.8V";
221 regulator-name = "VABB1_1.95V";
230 regulator-name = "VUOTG_3.0V";
238 regulator-name = "NFC_AVDD_1.8V";
246 regulator-name = "VABB2_1.95V";
255 regulator-name = "VHSIC_1.0V";
263 regulator-name = "VHSIC_1.8V";
271 regulator-name = "CAM_SENSOR_CORE_1.2V";
[all …]
/openbmc/phosphor-logging/lib/include/phosphor-logging/lg2/
H A Dconversion.hpp92 template <log_flags... Fs, unsigned_integral_except_bool V>
93 static auto log_convert(const char* h, log_flag<Fs...> f, V v) in log_convert()
109 template <log_flags... Fs, std::signed_integral V>
110 static auto log_convert(const char* h, log_flag<Fs...> f, V v) in log_convert()
125 template <log_flags... Fs, std::same_as<bool> V>
126 static auto log_convert(const char* h, log_flag<Fs...> f, V v) in log_convert()
145 template <log_flags... Fs, std::floating_point V>
146 static auto log_convert(const char* h, log_flag<Fs...> f, V v) in log_convert()
165 template <log_flags... Fs, sdbusplus_enum V>
166 static auto log_convert(const char* h, log_flag<Fs...> f, V v) in log_convert()
[all …]
/openbmc/qemu/docs/system/riscv/
H A Dmicroblaze-v-generic.rst1 Microblaze-V generic board (``amd-microblaze-v-generic``)
3 The AMD MicroBlaze™ V processor is a soft-core RISC-V processor IP for AMD
4 adaptive SoCs and FPGAs. The MicroBlaze™ V processor is based on the 32-bit (or
5 64-bit) RISC-V instruction set architecture (ISA) and contains interfaces
6 compatible with the classic MicroBlaze™ V processor (i.e it is a drop in
10 https://docs.amd.com/r/en-US/ug1629-microblaze-v-user-guide/MicroBlaze-V-Architecture
12 The MicroBlaze™ V generic board in QEMU has following supported devices:
22 The MicroBlaze™ V core in QEMU has the following configuration:
32 (xilinx_mbv32_defconfig) on the Microblaze-V generic board.
/openbmc/qemu/target/hexagon/mmvec/
H A Dmacros.h311 #define fVSATDW(U, V) fVSATW(((((long long)U) << 32) | fZXTN(32, 64, V))) argument
312 #define fVASL_SATHI(U, V) fVSATW(((U) << 1) | ((V) >> 31)) argument
313 #define fVUADDSAT(WIDTH, U, V) \ argument
314 fVSATUN(WIDTH, fZXTN(WIDTH, 2 * WIDTH, U) + fZXTN(WIDTH, 2 * WIDTH, V))
315 #define fVSADDSAT(WIDTH, U, V) \ argument
316 fVSATN(WIDTH, fSXTN(WIDTH, 2 * WIDTH, U) + fSXTN(WIDTH, 2 * WIDTH, V))
317 #define fVUSUBSAT(WIDTH, U, V) \ argument
318 fVSATUN(WIDTH, fZXTN(WIDTH, 2 * WIDTH, U) - fZXTN(WIDTH, 2 * WIDTH, V))
319 #define fVSSUBSAT(WIDTH, U, V) \ argument
320 fVSATN(WIDTH, fSXTN(WIDTH, 2 * WIDTH, U) - fSXTN(WIDTH, 2 * WIDTH, V))
[all …]
/openbmc/qemu/target/i386/tcg/
H A Ddecode-new.c.inc65 * The main difference is that the V, U and W types are extended to
73 * the V/U/H/W types to P/N/P/Q if there is no prefix, as well as changing
448 X86_OP_ENTRY3(MOVDQ, V,x, None,None, W,x, vex1), /* movdqa */
449 X86_OP_ENTRY3(MOVDQ, V,x, None,None, W,x, vex4_unal), /* movdqu */
459 X86_OP_ENTRY3(PSHUFD, V,x, W,x, I,b, vex4 avx2_256),
460 X86_OP_ENTRY3(PSHUFHW, V,x, W,x, I,b, vex4 avx2_256),
461 X86_OP_ENTRY3(PSHUFLW, V,x, W,x, I,b, vex4 avx2_256),
484 X86_OP_ENTRY3(EXTRQ_i, V,x, None,None, I,w, cpuid(SSE4A)), /* AMD extension */
486 X86_OP_ENTRY3(INSERTQ_i, V,x, U,x, I,w, cpuid(SSE4A)), /* AMD extension */
506 X86_OP_ENTRY3(MOVD_from, E,y, None,None, V,y, vex5),
[all …]
/openbmc/u-boot/arch/arm/mach-socfpga/
H A DKconfig49 bool "Altera SOCFPGA SoCDK (Arria V)"
53 bool "Altera SOCFPGA SoCDK (Cyclone V)"
57 bool "Devboards DBM-SoC1 (Cyclone V)"
61 bool "EBV SoCrates (Cyclone V)"
65 bool "IS1 (Cyclone V)"
69 bool "samtec VIN|ING FPGA (Cyclone V)"
74 bool "SR1500 (Cyclone V)"
82 bool "Terasic DE0-Nano-Atlas (Cyclone V)"
86 bool "Terasic DE10-Nano (Cyclone V)"
90 bool "Terasic DE1-SoC (Cyclone V)"
[all …]
/openbmc/u-boot/doc/
H A DREADME.qemu-riscv5 U-Boot on QEMU's 'virt' machine on RISC-V
8 QEMU for RISC-V supports a special 'virt' machine designed for emulation and
12 The QEMU virt machine models a generic RISC-V virtual machine with support for
15 configuration information to guest software. It implements RISC-V privileged
22 - For 32-bit RISC-V:
26 - For 64-bit RISC-V:
34 - For 32-bit RISC-V:
37 - For 64-bit RISC-V:
H A DREADME.ae3505 base on RISC-V architecture.
66 RISC-V # version
72 RISC-V # setenv ipaddr 10.0.4.200 ;
73 RISC-V # setenv serverip 10.0.4.97 ;
74 RISC-V # ping 10.0.4.97 ;
78 RISC-V # mmc rescan
79 RISC-V # fatls mmc 0:1
86 RISC-V # sf probe 0:0 50000000 0
89 RISC-V # sf test 0x100000 0x1000
101 RISC-V # fatload mmc 0:1 0x600000 u-boot-ae350-32.bin
[all …]
/openbmc/phosphor-virtual-sensor/src/
H A Dthresholds.hpp150 template <typename V>
151 auto alarmHighSignalAsserted(V value) in alarmHighSignalAsserted()
165 template <typename V>
166 auto alarmLowSignalAsserted(V value) in alarmLowSignalAsserted()
284 template <typename V>
285 auto alarmHighSignalAsserted(V value) in alarmHighSignalAsserted()
299 template <typename V>
300 auto alarmLowSignalAsserted(V value) in alarmLowSignalAsserted()
414 template <typename V>
415 auto alarmHighSignalAsserted(V value) in alarmHighSignalAsserted()
[all …]
/openbmc/openbmc/meta-openembedded/meta-oe/recipes-support/fbset/fbset-modes/om-gta01/
H A Dfb.modes4 # D: 26.000 MHz, H: 43.334 kHz, V: 65.657 Hz
11 # D: 26.000 MHz, H: 43.334 kHz, V: 65.657 Hz
18 # D: 8.475 MHz, H: 24.635 kHz, V: 75.569 Hz
25 # D: 8.475 MHz, H: 24.635 kHz, V: 75.569 Hz
/openbmc/qemu/docs/system/i386/
H A Dhyperv.rst1 Hyper-V Enlightenments
14 KVM on x86 implements Hyper-V Enlightenments for Windows guests. These features
15 make Windows and Hyper-V guests think they're running on top of a Hyper-V
16 compatible hypervisor and use Hyper-V specific features.
22 No Hyper-V enlightenments are enabled by default by either KVM or QEMU. In
32 When any set of the Hyper-V enlightenments is enabled, QEMU changes hypervisor
33 identification (CPUID 0x40000000..0x4000000A) to Hyper-V. KVM identification
74 Note: unlike under genuine Hyper-V, write to HV_X64_MSR_CRASH_CTL causes guest
78 Enables two Hyper-V-specific clocksources available to the guest: MSR-based
79 Hyper-V clocksource (HV_X64_MSR_TIME_REF_COUNT, 0x40000020) and Reference TSC
[all …]
/openbmc/u-boot/drivers/power/
H A DKconfig83 generic 3.3V IO voltage for external devices like the lcd-panal and
84 sdcard interfaces, etc. On most boards dcdc1 is undervolted to 3.0V to
100 On A10(s) / A13 / A20 boards dcdc2 is VDD-CPU and should be 1.4V.
101 On A31 boards dcdc2 is used for VDD-GPU and should be 1.2V.
102 On A23/A33 boards dcdc2 is used for VDD-SYS and should be 1.1V.
104 On A83T boards dcdc2 is used for VDD-CPUA(cluster 0) and should be 0.9V.
105 On R40 boards dcdc2 is VDD-CPU and should be 1.1V
119 should be 1.25V.
120 On A10s boards with an axp152 dcdc3 is VCC-DRAM and should be 1.5V.
121 On A23 / A31 / A33 boards dcdc3 is VDD-CPU and should be 1.2V.
[all …]
/openbmc/openbmc/poky/meta/conf/machine/include/riscv/
H A Dtune-riscv.inc3 TUNEVALID[riscv64] = "Enable 64-bit RISC-V optimizations"
4 TUNEVALID[riscv32] = "Enable 32-bit RISC-V optimizations"
6 TUNEVALID[riscv64nf] = "Enable 64-bit RISC-V optimizations no floating point"
7 TUNEVALID[riscv32nf] = "Enable 32-bit RISC-V optimizations no floating point"
9 TUNEVALID[riscv64nc] = "Enable 64-bit RISC-V optimizations without compressed instructions"
/openbmc/phosphor-inventory-manager/
H A Dfunctor.hpp138 template <typename T, typename U, typename V>
141 U&& member, V&& value) in setProperty()
148 value = std::forward<V>(value)](auto& b, auto& m) { in setProperty()
306 template <typename T, typename U, typename V>
339 GetProperty<V>&& getProperty = nullptr) : in PropertyCondition()
375 GetProperty<V> _getProperty;
391 template <typename T, typename V = InterfaceVariantType>
394 GetProperty<V>&& getProperty = nullptr) in propertyIs()
400 return PropertyCondition<T, U, V>(path, iface, property, in propertyIs()
/openbmc/qemu/docs/system/
H A Dtarget-riscv.rst1 .. _RISC-V-System-emulator:
3 RISC-V System emulator
6 QEMU can emulate both 32-bit and 64-bit RISC-V CPUs. Use the
7 ``qemu-system-riscv64`` executable to simulate a 64-bit RISC-V machine,
8 ``qemu-system-riscv32`` executable to simulate a 32-bit RISC-V machine.
10 QEMU has generally good support for RISC-V guests. It has support for
12 RISC-V hardware is much more widely varying than x86 hardware. RISC-V
25 For QEMU's RISC-V system emulation, you must specify which board
29 Because RISC-V systems differ so much and in fundamental ways, typically
56 Unfortunately many of the RISC-V boards QEMU supports are currently
[all …]
/openbmc/dbus-sensors/src/
H A DVariantVisitors.hpp72 template <std::integral V, std::integral U>
76 std::vector<V> operator()(const T& t) const in operator ()()
80 std::vector<V> output; in operator ()()
85 output.push_back(static_cast<V>(value)); in operator ()()
/openbmc/sdbusplus/include/sdbusplus/utility/
H A Dtuple_to_array.hpp28 template <typename V, typename... Types, std::size_t... I>
29 constexpr auto tuple_to_array(std::tuple<V, Types...>&& tuple, in tuple_to_array() argument
32 return std::array<V, sizeof...(I)>({ in tuple_to_array()
/openbmc/qemu/scripts/coccinelle/
H A Dremove_local_err.cocci10 idexpression V;
24 - V = F2(ARGS, &LOCAL_ERR);
26 + V = F2(ARGS, ERRP);
/openbmc/phosphor-fan-presence/control/json/actions/
H A Dset_parameter_from_group_max.cpp66 using V = std::decay_t<decltype(val)>; in run() typedef
67 if constexpr (!std::is_same_v<double, V> && in run()
68 !std::is_same_v<int32_t, V> && in run()
69 !std::is_same_v<int64_t, V>) in run()

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