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Searched refs:U_PM_ENABLE (Results 1 – 3 of 3) sorted by relevance

/openbmc/qemu/target/riscv/
H A Dcpu_bits.h794 #define U_PM_ENABLE (PM_ENABLE << U_OFFSET) macro
806 #define MMTE_U_PM_ENABLE U_PM_ENABLE
822 #define SMTE_U_PM_ENABLE U_PM_ENABLE
833 #define UMTE_U_PM_ENABLE U_PM_ENABLE
H A Dcpu_helper.c178 if (env->mmte & U_PM_ENABLE) { in riscv_cpu_update_mask()
H A Dcsr.c4469 if ((cpu_address_mode(env) == PRV_U) && (env->mmte & U_PM_ENABLE)) { in write_upmmask()
4555 if ((cpu_address_mode(env) == PRV_U) && (env->mmte & U_PM_ENABLE)) { in write_upmbase()