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Searched refs:UMC_BASE__INST5_SEG0 (Results 1 – 12 of 12) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/
H A Dnavi10_ip_offset.h806 #define UMC_BASE__INST5_SEG0 0 macro
H A Dnavi12_ip_offset.h1023 #define UMC_BASE__INST5_SEG0 0 macro
H A Ddimgrey_cavefish_ip_offset.h986 #define UMC_BASE__INST5_SEG0 0 macro
H A Dvega20_ip_offset.h875 #define UMC_BASE__INST5_SEG0 0 macro
H A Dnavi14_ip_offset.h1023 #define UMC_BASE__INST5_SEG0 0 macro
H A Dsienna_cichlid_ip_offset.h1072 #define UMC_BASE__INST5_SEG0 0x00154000 macro
H A Dbeige_goby_ip_offset.h1211 #define UMC_BASE__INST5_SEG0 0 macro
H A Drenoir_ip_offset.h1273 #define UMC_BASE__INST5_SEG0 0 macro
H A Dvangogh_ip_offset.h1383 #define UMC_BASE__INST5_SEG0 0 macro
H A Dyellow_carp_offset.h1302 #define UMC_BASE__INST5_SEG0 0 macro
H A Darct_ip_offset.h1460 #define UMC_BASE__INST5_SEG0 0x00013360 macro
H A Daldebaran_ip_offset.h1430 #define UMC_BASE__INST5_SEG0 0 macro