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Searched refs:UDCCSRW (Results 1 – 2 of 2) sorted by relevance

/openbmc/linux/arch/arm/mach-pxa/
H A Dpxa27x-udc.h137 #define UDCCSRW __REG(0x40600158) /* UDC Control/Status register - Endpoint W */ macro
/openbmc/u-boot/arch/arm/include/asm/arch-pxa/
H A Dpxa-regs.h681 #define UDCCSRW 0x40600158 /* UDC Control/Status register - Endpoint W */ macro