1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Driver for Motorola/Freescale IMX serial ports
4 *
5 * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
6 *
7 * Author: Sascha Hauer <sascha@saschahauer.de>
8 * Copyright (C) 2004 Pengutronix
9 */
10
11 #include <linux/module.h>
12 #include <linux/ioport.h>
13 #include <linux/init.h>
14 #include <linux/console.h>
15 #include <linux/sysrq.h>
16 #include <linux/platform_device.h>
17 #include <linux/tty.h>
18 #include <linux/tty_flip.h>
19 #include <linux/serial_core.h>
20 #include <linux/serial.h>
21 #include <linux/clk.h>
22 #include <linux/delay.h>
23 #include <linux/ktime.h>
24 #include <linux/pinctrl/consumer.h>
25 #include <linux/rational.h>
26 #include <linux/slab.h>
27 #include <linux/of.h>
28 #include <linux/io.h>
29 #include <linux/iopoll.h>
30 #include <linux/dma-mapping.h>
31
32 #include <asm/irq.h>
33 #include <linux/dma/imx-dma.h>
34
35 #include "serial_mctrl_gpio.h"
36
37 /* Register definitions */
38 #define URXD0 0x0 /* Receiver Register */
39 #define URTX0 0x40 /* Transmitter Register */
40 #define UCR1 0x80 /* Control Register 1 */
41 #define UCR2 0x84 /* Control Register 2 */
42 #define UCR3 0x88 /* Control Register 3 */
43 #define UCR4 0x8c /* Control Register 4 */
44 #define UFCR 0x90 /* FIFO Control Register */
45 #define USR1 0x94 /* Status Register 1 */
46 #define USR2 0x98 /* Status Register 2 */
47 #define UESC 0x9c /* Escape Character Register */
48 #define UTIM 0xa0 /* Escape Timer Register */
49 #define UBIR 0xa4 /* BRM Incremental Register */
50 #define UBMR 0xa8 /* BRM Modulator Register */
51 #define UBRC 0xac /* Baud Rate Count Register */
52 #define IMX21_ONEMS 0xb0 /* One Millisecond register */
53 #define IMX1_UTS 0xd0 /* UART Test Register on i.mx1 */
54 #define IMX21_UTS 0xb4 /* UART Test Register on all other i.mx*/
55
56 /* UART Control Register Bit Fields.*/
57 #define URXD_DUMMY_READ (1<<16)
58 #define URXD_CHARRDY (1<<15)
59 #define URXD_ERR (1<<14)
60 #define URXD_OVRRUN (1<<13)
61 #define URXD_FRMERR (1<<12)
62 #define URXD_BRK (1<<11)
63 #define URXD_PRERR (1<<10)
64 #define URXD_RX_DATA (0xFF<<0)
65 #define UCR1_ADEN (1<<15) /* Auto detect interrupt */
66 #define UCR1_ADBR (1<<14) /* Auto detect baud rate */
67 #define UCR1_TRDYEN (1<<13) /* Transmitter ready interrupt enable */
68 #define UCR1_IDEN (1<<12) /* Idle condition interrupt */
69 #define UCR1_ICD_REG(x) (((x) & 3) << 10) /* idle condition detect */
70 #define UCR1_RRDYEN (1<<9) /* Recv ready interrupt enable */
71 #define UCR1_RXDMAEN (1<<8) /* Recv ready DMA enable */
72 #define UCR1_IREN (1<<7) /* Infrared interface enable */
73 #define UCR1_TXMPTYEN (1<<6) /* Transimitter empty interrupt enable */
74 #define UCR1_RTSDEN (1<<5) /* RTS delta interrupt enable */
75 #define UCR1_SNDBRK (1<<4) /* Send break */
76 #define UCR1_TXDMAEN (1<<3) /* Transmitter ready DMA enable */
77 #define IMX1_UCR1_UARTCLKEN (1<<2) /* UART clock enabled, i.mx1 only */
78 #define UCR1_ATDMAEN (1<<2) /* Aging DMA Timer Enable */
79 #define UCR1_DOZE (1<<1) /* Doze */
80 #define UCR1_UARTEN (1<<0) /* UART enabled */
81 #define UCR2_ESCI (1<<15) /* Escape seq interrupt enable */
82 #define UCR2_IRTS (1<<14) /* Ignore RTS pin */
83 #define UCR2_CTSC (1<<13) /* CTS pin control */
84 #define UCR2_CTS (1<<12) /* Clear to send */
85 #define UCR2_ESCEN (1<<11) /* Escape enable */
86 #define UCR2_PREN (1<<8) /* Parity enable */
87 #define UCR2_PROE (1<<7) /* Parity odd/even */
88 #define UCR2_STPB (1<<6) /* Stop */
89 #define UCR2_WS (1<<5) /* Word size */
90 #define UCR2_RTSEN (1<<4) /* Request to send interrupt enable */
91 #define UCR2_ATEN (1<<3) /* Aging Timer Enable */
92 #define UCR2_TXEN (1<<2) /* Transmitter enabled */
93 #define UCR2_RXEN (1<<1) /* Receiver enabled */
94 #define UCR2_SRST (1<<0) /* SW reset */
95 #define UCR3_DTREN (1<<13) /* DTR interrupt enable */
96 #define UCR3_PARERREN (1<<12) /* Parity enable */
97 #define UCR3_FRAERREN (1<<11) /* Frame error interrupt enable */
98 #define UCR3_DSR (1<<10) /* Data set ready */
99 #define UCR3_DCD (1<<9) /* Data carrier detect */
100 #define UCR3_RI (1<<8) /* Ring indicator */
101 #define UCR3_ADNIMP (1<<7) /* Autobaud Detection Not Improved */
102 #define UCR3_RXDSEN (1<<6) /* Receive status interrupt enable */
103 #define UCR3_AIRINTEN (1<<5) /* Async IR wake interrupt enable */
104 #define UCR3_AWAKEN (1<<4) /* Async wake interrupt enable */
105 #define UCR3_DTRDEN (1<<3) /* Data Terminal Ready Delta Enable. */
106 #define IMX21_UCR3_RXDMUXSEL (1<<2) /* RXD Muxed Input Select */
107 #define UCR3_INVT (1<<1) /* Inverted Infrared transmission */
108 #define UCR3_BPEN (1<<0) /* Preset registers enable */
109 #define UCR4_CTSTL_SHF 10 /* CTS trigger level shift */
110 #define UCR4_CTSTL_MASK 0x3F /* CTS trigger is 6 bits wide */
111 #define UCR4_INVR (1<<9) /* Inverted infrared reception */
112 #define UCR4_ENIRI (1<<8) /* Serial infrared interrupt enable */
113 #define UCR4_WKEN (1<<7) /* Wake interrupt enable */
114 #define UCR4_REF16 (1<<6) /* Ref freq 16 MHz */
115 #define UCR4_IDDMAEN (1<<6) /* DMA IDLE Condition Detected */
116 #define UCR4_IRSC (1<<5) /* IR special case */
117 #define UCR4_TCEN (1<<3) /* Transmit complete interrupt enable */
118 #define UCR4_BKEN (1<<2) /* Break condition interrupt enable */
119 #define UCR4_OREN (1<<1) /* Receiver overrun interrupt enable */
120 #define UCR4_DREN (1<<0) /* Recv data ready interrupt enable */
121 #define UFCR_RXTL_SHF 0 /* Receiver trigger level shift */
122 #define UFCR_DCEDTE (1<<6) /* DCE/DTE mode select */
123 #define UFCR_RFDIV (7<<7) /* Reference freq divider mask */
124 #define UFCR_RFDIV_REG(x) (((x) < 7 ? 6 - (x) : 6) << 7)
125 #define UFCR_TXTL_SHF 10 /* Transmitter trigger level shift */
126 #define USR1_PARITYERR (1<<15) /* Parity error interrupt flag */
127 #define USR1_RTSS (1<<14) /* RTS pin status */
128 #define USR1_TRDY (1<<13) /* Transmitter ready interrupt/dma flag */
129 #define USR1_RTSD (1<<12) /* RTS delta */
130 #define USR1_ESCF (1<<11) /* Escape seq interrupt flag */
131 #define USR1_FRAMERR (1<<10) /* Frame error interrupt flag */
132 #define USR1_RRDY (1<<9) /* Receiver ready interrupt/dma flag */
133 #define USR1_AGTIM (1<<8) /* Ageing timer interrupt flag */
134 #define USR1_DTRD (1<<7) /* DTR Delta */
135 #define USR1_RXDS (1<<6) /* Receiver idle interrupt flag */
136 #define USR1_AIRINT (1<<5) /* Async IR wake interrupt flag */
137 #define USR1_AWAKE (1<<4) /* Aysnc wake interrupt flag */
138 #define USR2_ADET (1<<15) /* Auto baud rate detect complete */
139 #define USR2_TXFE (1<<14) /* Transmit buffer FIFO empty */
140 #define USR2_DTRF (1<<13) /* DTR edge interrupt flag */
141 #define USR2_IDLE (1<<12) /* Idle condition */
142 #define USR2_RIDELT (1<<10) /* Ring Interrupt Delta */
143 #define USR2_RIIN (1<<9) /* Ring Indicator Input */
144 #define USR2_IRINT (1<<8) /* Serial infrared interrupt flag */
145 #define USR2_WAKE (1<<7) /* Wake */
146 #define USR2_DCDIN (1<<5) /* Data Carrier Detect Input */
147 #define USR2_RTSF (1<<4) /* RTS edge interrupt flag */
148 #define USR2_TXDC (1<<3) /* Transmitter complete */
149 #define USR2_BRCD (1<<2) /* Break condition */
150 #define USR2_ORE (1<<1) /* Overrun error */
151 #define USR2_RDR (1<<0) /* Recv data ready */
152 #define UTS_FRCPERR (1<<13) /* Force parity error */
153 #define UTS_LOOP (1<<12) /* Loop tx and rx */
154 #define UTS_TXEMPTY (1<<6) /* TxFIFO empty */
155 #define UTS_RXEMPTY (1<<5) /* RxFIFO empty */
156 #define UTS_TXFULL (1<<4) /* TxFIFO full */
157 #define UTS_RXFULL (1<<3) /* RxFIFO full */
158 #define UTS_SOFTRST (1<<0) /* Software reset */
159
160 /* We've been assigned a range on the "Low-density serial ports" major */
161 #define SERIAL_IMX_MAJOR 207
162 #define MINOR_START 16
163 #define DEV_NAME "ttymxc"
164
165 /*
166 * This determines how often we check the modem status signals
167 * for any change. They generally aren't connected to an IRQ
168 * so we have to poll them. We also check immediately before
169 * filling the TX fifo incase CTS has been dropped.
170 */
171 #define MCTRL_TIMEOUT (250*HZ/1000)
172
173 #define DRIVER_NAME "IMX-uart"
174
175 #define UART_NR 8
176
177 /* i.MX21 type uart runs on all i.mx except i.MX1 and i.MX6q */
178 enum imx_uart_type {
179 IMX1_UART,
180 IMX21_UART,
181 IMX53_UART,
182 IMX6Q_UART,
183 };
184
185 /* device type dependent stuff */
186 struct imx_uart_data {
187 unsigned uts_reg;
188 enum imx_uart_type devtype;
189 };
190
191 enum imx_tx_state {
192 OFF,
193 WAIT_AFTER_RTS,
194 SEND,
195 WAIT_AFTER_SEND,
196 };
197
198 struct imx_port {
199 struct uart_port port;
200 struct timer_list timer;
201 unsigned int old_status;
202 unsigned int have_rtscts:1;
203 unsigned int have_rtsgpio:1;
204 unsigned int dte_mode:1;
205 unsigned int inverted_tx:1;
206 unsigned int inverted_rx:1;
207 struct clk *clk_ipg;
208 struct clk *clk_per;
209 const struct imx_uart_data *devdata;
210
211 struct mctrl_gpios *gpios;
212
213 /* counter to stop 0xff flood */
214 int idle_counter;
215
216 /* DMA fields */
217 unsigned int dma_is_enabled:1;
218 unsigned int dma_is_rxing:1;
219 unsigned int dma_is_txing:1;
220 struct dma_chan *dma_chan_rx, *dma_chan_tx;
221 struct scatterlist rx_sgl, tx_sgl[2];
222 void *rx_buf;
223 struct circ_buf rx_ring;
224 unsigned int rx_buf_size;
225 unsigned int rx_period_length;
226 unsigned int rx_periods;
227 dma_cookie_t rx_cookie;
228 unsigned int tx_bytes;
229 unsigned int dma_tx_nents;
230 unsigned int saved_reg[10];
231 bool context_saved;
232
233 enum imx_tx_state tx_state;
234 struct hrtimer trigger_start_tx;
235 struct hrtimer trigger_stop_tx;
236 };
237
238 struct imx_port_ucrs {
239 unsigned int ucr1;
240 unsigned int ucr2;
241 unsigned int ucr3;
242 };
243
244 static struct imx_uart_data imx_uart_devdata[] = {
245 [IMX1_UART] = {
246 .uts_reg = IMX1_UTS,
247 .devtype = IMX1_UART,
248 },
249 [IMX21_UART] = {
250 .uts_reg = IMX21_UTS,
251 .devtype = IMX21_UART,
252 },
253 [IMX53_UART] = {
254 .uts_reg = IMX21_UTS,
255 .devtype = IMX53_UART,
256 },
257 [IMX6Q_UART] = {
258 .uts_reg = IMX21_UTS,
259 .devtype = IMX6Q_UART,
260 },
261 };
262
263 static const struct of_device_id imx_uart_dt_ids[] = {
264 { .compatible = "fsl,imx6q-uart", .data = &imx_uart_devdata[IMX6Q_UART], },
265 { .compatible = "fsl,imx53-uart", .data = &imx_uart_devdata[IMX53_UART], },
266 { .compatible = "fsl,imx1-uart", .data = &imx_uart_devdata[IMX1_UART], },
267 { .compatible = "fsl,imx21-uart", .data = &imx_uart_devdata[IMX21_UART], },
268 { /* sentinel */ }
269 };
270 MODULE_DEVICE_TABLE(of, imx_uart_dt_ids);
271
imx_uart_writel(struct imx_port * sport,u32 val,u32 offset)272 static inline void imx_uart_writel(struct imx_port *sport, u32 val, u32 offset)
273 {
274 writel(val, sport->port.membase + offset);
275 }
276
imx_uart_readl(struct imx_port * sport,u32 offset)277 static inline u32 imx_uart_readl(struct imx_port *sport, u32 offset)
278 {
279 return readl(sport->port.membase + offset);
280 }
281
imx_uart_uts_reg(struct imx_port * sport)282 static inline unsigned imx_uart_uts_reg(struct imx_port *sport)
283 {
284 return sport->devdata->uts_reg;
285 }
286
imx_uart_is_imx1(struct imx_port * sport)287 static inline int imx_uart_is_imx1(struct imx_port *sport)
288 {
289 return sport->devdata->devtype == IMX1_UART;
290 }
291
292 /*
293 * Save and restore functions for UCR1, UCR2 and UCR3 registers
294 */
295 #if IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE)
imx_uart_ucrs_save(struct imx_port * sport,struct imx_port_ucrs * ucr)296 static void imx_uart_ucrs_save(struct imx_port *sport,
297 struct imx_port_ucrs *ucr)
298 {
299 /* save control registers */
300 ucr->ucr1 = imx_uart_readl(sport, UCR1);
301 ucr->ucr2 = imx_uart_readl(sport, UCR2);
302 ucr->ucr3 = imx_uart_readl(sport, UCR3);
303 }
304
imx_uart_ucrs_restore(struct imx_port * sport,struct imx_port_ucrs * ucr)305 static void imx_uart_ucrs_restore(struct imx_port *sport,
306 struct imx_port_ucrs *ucr)
307 {
308 /* restore control registers */
309 imx_uart_writel(sport, ucr->ucr1, UCR1);
310 imx_uart_writel(sport, ucr->ucr2, UCR2);
311 imx_uart_writel(sport, ucr->ucr3, UCR3);
312 }
313 #endif
314
315 /* called with port.lock taken and irqs caller dependent */
imx_uart_rts_active(struct imx_port * sport,u32 * ucr2)316 static void imx_uart_rts_active(struct imx_port *sport, u32 *ucr2)
317 {
318 *ucr2 &= ~(UCR2_CTSC | UCR2_CTS);
319
320 mctrl_gpio_set(sport->gpios, sport->port.mctrl | TIOCM_RTS);
321 }
322
323 /* called with port.lock taken and irqs caller dependent */
imx_uart_rts_inactive(struct imx_port * sport,u32 * ucr2)324 static void imx_uart_rts_inactive(struct imx_port *sport, u32 *ucr2)
325 {
326 *ucr2 &= ~UCR2_CTSC;
327 *ucr2 |= UCR2_CTS;
328
329 mctrl_gpio_set(sport->gpios, sport->port.mctrl & ~TIOCM_RTS);
330 }
331
start_hrtimer_ms(struct hrtimer * hrt,unsigned long msec)332 static void start_hrtimer_ms(struct hrtimer *hrt, unsigned long msec)
333 {
334 hrtimer_start(hrt, ms_to_ktime(msec), HRTIMER_MODE_REL);
335 }
336
337 /* called with port.lock taken and irqs off */
imx_uart_soft_reset(struct imx_port * sport)338 static void imx_uart_soft_reset(struct imx_port *sport)
339 {
340 int i = 10;
341 u32 ucr2, ubir, ubmr, uts;
342
343 /*
344 * According to the Reference Manual description of the UART SRST bit:
345 *
346 * "Reset the transmit and receive state machines,
347 * all FIFOs and register USR1, USR2, UBIR, UBMR, UBRC, URXD, UTXD
348 * and UTS[6-3]".
349 *
350 * We don't need to restore the old values from USR1, USR2, URXD and
351 * UTXD. UBRC is read only, so only save/restore the other three
352 * registers.
353 */
354 ubir = imx_uart_readl(sport, UBIR);
355 ubmr = imx_uart_readl(sport, UBMR);
356 uts = imx_uart_readl(sport, IMX21_UTS);
357
358 ucr2 = imx_uart_readl(sport, UCR2);
359 imx_uart_writel(sport, ucr2 & ~UCR2_SRST, UCR2);
360
361 while (!(imx_uart_readl(sport, UCR2) & UCR2_SRST) && (--i > 0))
362 udelay(1);
363
364 /* Restore the registers */
365 imx_uart_writel(sport, ubir, UBIR);
366 imx_uart_writel(sport, ubmr, UBMR);
367 imx_uart_writel(sport, uts, IMX21_UTS);
368
369 sport->idle_counter = 0;
370 }
371
imx_uart_disable_loopback_rs485(struct imx_port * sport)372 static void imx_uart_disable_loopback_rs485(struct imx_port *sport)
373 {
374 unsigned int uts;
375
376 /* See SER_RS485_ENABLED/UTS_LOOP comment in imx_uart_probe() */
377 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport));
378 uts &= ~UTS_LOOP;
379 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
380 }
381
382 /* called with port.lock taken and irqs off */
imx_uart_start_rx(struct uart_port * port)383 static void imx_uart_start_rx(struct uart_port *port)
384 {
385 struct imx_port *sport = (struct imx_port *)port;
386 unsigned int ucr1, ucr2;
387
388 ucr1 = imx_uart_readl(sport, UCR1);
389 ucr2 = imx_uart_readl(sport, UCR2);
390
391 ucr2 |= UCR2_RXEN;
392
393 if (sport->dma_is_enabled) {
394 ucr1 |= UCR1_RXDMAEN | UCR1_ATDMAEN;
395 } else {
396 ucr1 |= UCR1_RRDYEN;
397 ucr2 |= UCR2_ATEN;
398 }
399
400 /* Write UCR2 first as it includes RXEN */
401 imx_uart_writel(sport, ucr2, UCR2);
402 imx_uart_writel(sport, ucr1, UCR1);
403 imx_uart_disable_loopback_rs485(sport);
404 }
405
406 /* called with port.lock taken and irqs off */
imx_uart_stop_tx(struct uart_port * port)407 static void imx_uart_stop_tx(struct uart_port *port)
408 {
409 struct imx_port *sport = (struct imx_port *)port;
410 u32 ucr1, ucr4, usr2;
411
412 if (sport->tx_state == OFF)
413 return;
414
415 /*
416 * We are maybe in the SMP context, so if the DMA TX thread is running
417 * on other cpu, we have to wait for it to finish.
418 */
419 if (sport->dma_is_txing)
420 return;
421
422 ucr1 = imx_uart_readl(sport, UCR1);
423 imx_uart_writel(sport, ucr1 & ~UCR1_TRDYEN, UCR1);
424
425 ucr4 = imx_uart_readl(sport, UCR4);
426 usr2 = imx_uart_readl(sport, USR2);
427 if ((!(usr2 & USR2_TXDC)) && (ucr4 & UCR4_TCEN)) {
428 /* The shifter is still busy, so retry once TC triggers */
429 return;
430 }
431
432 ucr4 &= ~UCR4_TCEN;
433 imx_uart_writel(sport, ucr4, UCR4);
434
435 /* in rs485 mode disable transmitter */
436 if (port->rs485.flags & SER_RS485_ENABLED) {
437 if (sport->tx_state == SEND) {
438 sport->tx_state = WAIT_AFTER_SEND;
439
440 if (port->rs485.delay_rts_after_send > 0) {
441 start_hrtimer_ms(&sport->trigger_stop_tx,
442 port->rs485.delay_rts_after_send);
443 return;
444 }
445
446 /* continue without any delay */
447 }
448
449 if (sport->tx_state == WAIT_AFTER_RTS ||
450 sport->tx_state == WAIT_AFTER_SEND) {
451 u32 ucr2;
452
453 hrtimer_try_to_cancel(&sport->trigger_start_tx);
454
455 ucr2 = imx_uart_readl(sport, UCR2);
456 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
457 imx_uart_rts_active(sport, &ucr2);
458 else
459 imx_uart_rts_inactive(sport, &ucr2);
460 imx_uart_writel(sport, ucr2, UCR2);
461
462 if (!port->rs485_rx_during_tx_gpio)
463 imx_uart_start_rx(port);
464
465 sport->tx_state = OFF;
466 }
467 } else {
468 sport->tx_state = OFF;
469 }
470 }
471
imx_uart_stop_rx_with_loopback_ctrl(struct uart_port * port,bool loopback)472 static void imx_uart_stop_rx_with_loopback_ctrl(struct uart_port *port, bool loopback)
473 {
474 struct imx_port *sport = (struct imx_port *)port;
475 u32 ucr1, ucr2, ucr4, uts;
476
477 ucr1 = imx_uart_readl(sport, UCR1);
478 ucr2 = imx_uart_readl(sport, UCR2);
479 ucr4 = imx_uart_readl(sport, UCR4);
480
481 if (sport->dma_is_enabled) {
482 ucr1 &= ~(UCR1_RXDMAEN | UCR1_ATDMAEN);
483 } else {
484 ucr1 &= ~UCR1_RRDYEN;
485 ucr2 &= ~UCR2_ATEN;
486 ucr4 &= ~UCR4_OREN;
487 }
488 imx_uart_writel(sport, ucr1, UCR1);
489 imx_uart_writel(sport, ucr4, UCR4);
490
491 /* See SER_RS485_ENABLED/UTS_LOOP comment in imx_uart_probe() */
492 if (port->rs485.flags & SER_RS485_ENABLED &&
493 port->rs485.flags & SER_RS485_RTS_ON_SEND &&
494 sport->have_rtscts && !sport->have_rtsgpio && loopback) {
495 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport));
496 uts |= UTS_LOOP;
497 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
498 ucr2 |= UCR2_RXEN;
499 } else {
500 ucr2 &= ~UCR2_RXEN;
501 }
502
503 imx_uart_writel(sport, ucr2, UCR2);
504 }
505
506 /* called with port.lock taken and irqs off */
imx_uart_stop_rx(struct uart_port * port)507 static void imx_uart_stop_rx(struct uart_port *port)
508 {
509 /*
510 * Stop RX and enable loopback in order to make sure RS485 bus
511 * is not blocked. Se comment in imx_uart_probe().
512 */
513 imx_uart_stop_rx_with_loopback_ctrl(port, true);
514 }
515
516 /* called with port.lock taken and irqs off */
imx_uart_enable_ms(struct uart_port * port)517 static void imx_uart_enable_ms(struct uart_port *port)
518 {
519 struct imx_port *sport = (struct imx_port *)port;
520
521 mod_timer(&sport->timer, jiffies);
522
523 mctrl_gpio_enable_ms(sport->gpios);
524 }
525
526 static void imx_uart_dma_tx(struct imx_port *sport);
527
528 /* called with port.lock taken and irqs off */
imx_uart_transmit_buffer(struct imx_port * sport)529 static inline void imx_uart_transmit_buffer(struct imx_port *sport)
530 {
531 struct circ_buf *xmit = &sport->port.state->xmit;
532
533 if (sport->port.x_char) {
534 /* Send next char */
535 imx_uart_writel(sport, sport->port.x_char, URTX0);
536 sport->port.icount.tx++;
537 sport->port.x_char = 0;
538 return;
539 }
540
541 if (uart_circ_empty(xmit) || uart_tx_stopped(&sport->port)) {
542 imx_uart_stop_tx(&sport->port);
543 return;
544 }
545
546 if (sport->dma_is_enabled) {
547 u32 ucr1;
548 /*
549 * We've just sent a X-char Ensure the TX DMA is enabled
550 * and the TX IRQ is disabled.
551 **/
552 ucr1 = imx_uart_readl(sport, UCR1);
553 ucr1 &= ~UCR1_TRDYEN;
554 if (sport->dma_is_txing) {
555 ucr1 |= UCR1_TXDMAEN;
556 imx_uart_writel(sport, ucr1, UCR1);
557 } else {
558 imx_uart_writel(sport, ucr1, UCR1);
559 imx_uart_dma_tx(sport);
560 }
561
562 return;
563 }
564
565 while (!uart_circ_empty(xmit) &&
566 !(imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)) {
567 /* send xmit->buf[xmit->tail]
568 * out the port here */
569 imx_uart_writel(sport, xmit->buf[xmit->tail], URTX0);
570 uart_xmit_advance(&sport->port, 1);
571 }
572
573 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
574 uart_write_wakeup(&sport->port);
575
576 if (uart_circ_empty(xmit))
577 imx_uart_stop_tx(&sport->port);
578 }
579
imx_uart_dma_tx_callback(void * data)580 static void imx_uart_dma_tx_callback(void *data)
581 {
582 struct imx_port *sport = data;
583 struct scatterlist *sgl = &sport->tx_sgl[0];
584 struct circ_buf *xmit = &sport->port.state->xmit;
585 unsigned long flags;
586 u32 ucr1;
587
588 spin_lock_irqsave(&sport->port.lock, flags);
589
590 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
591
592 ucr1 = imx_uart_readl(sport, UCR1);
593 ucr1 &= ~UCR1_TXDMAEN;
594 imx_uart_writel(sport, ucr1, UCR1);
595
596 uart_xmit_advance(&sport->port, sport->tx_bytes);
597
598 dev_dbg(sport->port.dev, "we finish the TX DMA.\n");
599
600 sport->dma_is_txing = 0;
601
602 if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
603 uart_write_wakeup(&sport->port);
604
605 if (!uart_circ_empty(xmit) && !uart_tx_stopped(&sport->port))
606 imx_uart_dma_tx(sport);
607 else if (sport->port.rs485.flags & SER_RS485_ENABLED) {
608 u32 ucr4 = imx_uart_readl(sport, UCR4);
609 ucr4 |= UCR4_TCEN;
610 imx_uart_writel(sport, ucr4, UCR4);
611 }
612
613 spin_unlock_irqrestore(&sport->port.lock, flags);
614 }
615
616 /* called with port.lock taken and irqs off */
imx_uart_dma_tx(struct imx_port * sport)617 static void imx_uart_dma_tx(struct imx_port *sport)
618 {
619 struct circ_buf *xmit = &sport->port.state->xmit;
620 struct scatterlist *sgl = sport->tx_sgl;
621 struct dma_async_tx_descriptor *desc;
622 struct dma_chan *chan = sport->dma_chan_tx;
623 struct device *dev = sport->port.dev;
624 u32 ucr1, ucr4;
625 int ret;
626
627 if (sport->dma_is_txing)
628 return;
629
630 ucr4 = imx_uart_readl(sport, UCR4);
631 ucr4 &= ~UCR4_TCEN;
632 imx_uart_writel(sport, ucr4, UCR4);
633
634 sport->tx_bytes = uart_circ_chars_pending(xmit);
635
636 if (xmit->tail < xmit->head || xmit->head == 0) {
637 sport->dma_tx_nents = 1;
638 sg_init_one(sgl, xmit->buf + xmit->tail, sport->tx_bytes);
639 } else {
640 sport->dma_tx_nents = 2;
641 sg_init_table(sgl, 2);
642 sg_set_buf(sgl, xmit->buf + xmit->tail,
643 UART_XMIT_SIZE - xmit->tail);
644 sg_set_buf(sgl + 1, xmit->buf, xmit->head);
645 }
646
647 ret = dma_map_sg(dev, sgl, sport->dma_tx_nents, DMA_TO_DEVICE);
648 if (ret == 0) {
649 dev_err(dev, "DMA mapping error for TX.\n");
650 return;
651 }
652 desc = dmaengine_prep_slave_sg(chan, sgl, ret,
653 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
654 if (!desc) {
655 dma_unmap_sg(dev, sgl, sport->dma_tx_nents,
656 DMA_TO_DEVICE);
657 dev_err(dev, "We cannot prepare for the TX slave dma!\n");
658 return;
659 }
660 desc->callback = imx_uart_dma_tx_callback;
661 desc->callback_param = sport;
662
663 dev_dbg(dev, "TX: prepare to send %lu bytes by DMA.\n",
664 uart_circ_chars_pending(xmit));
665
666 ucr1 = imx_uart_readl(sport, UCR1);
667 ucr1 |= UCR1_TXDMAEN;
668 imx_uart_writel(sport, ucr1, UCR1);
669
670 /* fire it */
671 sport->dma_is_txing = 1;
672 dmaengine_submit(desc);
673 dma_async_issue_pending(chan);
674 return;
675 }
676
677 /* called with port.lock taken and irqs off */
imx_uart_start_tx(struct uart_port * port)678 static void imx_uart_start_tx(struct uart_port *port)
679 {
680 struct imx_port *sport = (struct imx_port *)port;
681 u32 ucr1;
682
683 if (!sport->port.x_char && uart_circ_empty(&port->state->xmit))
684 return;
685
686 /*
687 * We cannot simply do nothing here if sport->tx_state == SEND already
688 * because UCR1_TXMPTYEN might already have been cleared in
689 * imx_uart_stop_tx(), but tx_state is still SEND.
690 */
691
692 if (port->rs485.flags & SER_RS485_ENABLED) {
693 if (sport->tx_state == OFF) {
694 u32 ucr2 = imx_uart_readl(sport, UCR2);
695 if (port->rs485.flags & SER_RS485_RTS_ON_SEND)
696 imx_uart_rts_active(sport, &ucr2);
697 else
698 imx_uart_rts_inactive(sport, &ucr2);
699 imx_uart_writel(sport, ucr2, UCR2);
700
701 /*
702 * Since we are about to transmit we can not stop RX
703 * with loopback enabled because that will make our
704 * transmitted data being just looped to RX.
705 */
706 if (!(port->rs485.flags & SER_RS485_RX_DURING_TX) &&
707 !port->rs485_rx_during_tx_gpio)
708 imx_uart_stop_rx_with_loopback_ctrl(port, false);
709
710 sport->tx_state = WAIT_AFTER_RTS;
711
712 if (port->rs485.delay_rts_before_send > 0) {
713 start_hrtimer_ms(&sport->trigger_start_tx,
714 port->rs485.delay_rts_before_send);
715 return;
716 }
717
718 /* continue without any delay */
719 }
720
721 if (sport->tx_state == WAIT_AFTER_SEND
722 || sport->tx_state == WAIT_AFTER_RTS) {
723
724 hrtimer_try_to_cancel(&sport->trigger_stop_tx);
725
726 /*
727 * Enable transmitter and shifter empty irq only if DMA
728 * is off. In the DMA case this is done in the
729 * tx-callback.
730 */
731 if (!sport->dma_is_enabled) {
732 u32 ucr4 = imx_uart_readl(sport, UCR4);
733 ucr4 |= UCR4_TCEN;
734 imx_uart_writel(sport, ucr4, UCR4);
735 }
736
737 sport->tx_state = SEND;
738 }
739 } else {
740 sport->tx_state = SEND;
741 }
742
743 if (!sport->dma_is_enabled) {
744 ucr1 = imx_uart_readl(sport, UCR1);
745 imx_uart_writel(sport, ucr1 | UCR1_TRDYEN, UCR1);
746 }
747
748 if (sport->dma_is_enabled) {
749 if (sport->port.x_char) {
750 /* We have X-char to send, so enable TX IRQ and
751 * disable TX DMA to let TX interrupt to send X-char */
752 ucr1 = imx_uart_readl(sport, UCR1);
753 ucr1 &= ~UCR1_TXDMAEN;
754 ucr1 |= UCR1_TRDYEN;
755 imx_uart_writel(sport, ucr1, UCR1);
756 return;
757 }
758
759 if (!uart_circ_empty(&port->state->xmit) &&
760 !uart_tx_stopped(port))
761 imx_uart_dma_tx(sport);
762 return;
763 }
764 }
765
__imx_uart_rtsint(int irq,void * dev_id)766 static irqreturn_t __imx_uart_rtsint(int irq, void *dev_id)
767 {
768 struct imx_port *sport = dev_id;
769 u32 usr1;
770
771 imx_uart_writel(sport, USR1_RTSD, USR1);
772 usr1 = imx_uart_readl(sport, USR1) & USR1_RTSS;
773 uart_handle_cts_change(&sport->port, usr1);
774 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
775
776 return IRQ_HANDLED;
777 }
778
imx_uart_rtsint(int irq,void * dev_id)779 static irqreturn_t imx_uart_rtsint(int irq, void *dev_id)
780 {
781 struct imx_port *sport = dev_id;
782 irqreturn_t ret;
783
784 spin_lock(&sport->port.lock);
785
786 ret = __imx_uart_rtsint(irq, dev_id);
787
788 spin_unlock(&sport->port.lock);
789
790 return ret;
791 }
792
imx_uart_txint(int irq,void * dev_id)793 static irqreturn_t imx_uart_txint(int irq, void *dev_id)
794 {
795 struct imx_port *sport = dev_id;
796
797 spin_lock(&sport->port.lock);
798 imx_uart_transmit_buffer(sport);
799 spin_unlock(&sport->port.lock);
800 return IRQ_HANDLED;
801 }
802
803 /* Check if hardware Rx flood is in progress, and issue soft reset to stop it.
804 * This is to be called from Rx ISRs only when some bytes were actually
805 * received.
806 *
807 * A way to reproduce the flood (checked on iMX6SX) is: open iMX UART at 9600
808 * 8N1, and from external source send 0xf0 char at 115200 8N1. In about 90% of
809 * cases this starts a flood of "receiving" of 0xff characters by the iMX6 UART
810 * that is terminated by any activity on RxD line, or could be stopped by
811 * issuing soft reset to the UART (just stop/start of RX does not help). Note
812 * that what we do here is sending isolated start bit about 2.4 times shorter
813 * than it is to be on UART configured baud rate.
814 */
imx_uart_check_flood(struct imx_port * sport,u32 usr2)815 static void imx_uart_check_flood(struct imx_port *sport, u32 usr2)
816 {
817 /* To detect hardware 0xff flood we monitor RxD line between RX
818 * interrupts to isolate "receiving" of char(s) with no activity
819 * on RxD line, that'd never happen on actual data transfers.
820 *
821 * We use USR2_WAKE bit to check for activity on RxD line, but we have a
822 * race here if we clear USR2_WAKE when receiving of a char is in
823 * progress, so we might get RX interrupt later with USR2_WAKE bit
824 * cleared. Note though that as we don't try to clear USR2_WAKE when we
825 * detected no activity, this race may hide actual activity only once.
826 *
827 * Yet another case where receive interrupt may occur without RxD
828 * activity is expiration of aging timer, so we consider this as well.
829 *
830 * We use 'idle_counter' to ensure that we got at least so many RX
831 * interrupts without any detected activity on RxD line. 2 cases
832 * described plus 1 to be on the safe side gives us a margin of 3,
833 * below. In practice I was not able to produce a false positive to
834 * induce soft reset at regular data transfers even using 1 as the
835 * margin, so 3 is actually very strong.
836 *
837 * We count interrupts, not chars in 'idle-counter' for simplicity.
838 */
839
840 if (usr2 & USR2_WAKE) {
841 imx_uart_writel(sport, USR2_WAKE, USR2);
842 sport->idle_counter = 0;
843 } else if (++sport->idle_counter > 3) {
844 dev_warn(sport->port.dev, "RX flood detected: soft reset.");
845 imx_uart_soft_reset(sport); /* also clears 'sport->idle_counter' */
846 }
847 }
848
__imx_uart_rxint(int irq,void * dev_id)849 static irqreturn_t __imx_uart_rxint(int irq, void *dev_id)
850 {
851 struct imx_port *sport = dev_id;
852 struct tty_port *port = &sport->port.state->port;
853 u32 usr2, rx;
854
855 /* If we received something, check for 0xff flood */
856 usr2 = imx_uart_readl(sport, USR2);
857 if (usr2 & USR2_RDR)
858 imx_uart_check_flood(sport, usr2);
859
860 while ((rx = imx_uart_readl(sport, URXD0)) & URXD_CHARRDY) {
861 unsigned int flg = TTY_NORMAL;
862 sport->port.icount.rx++;
863
864 if (unlikely(rx & URXD_ERR)) {
865 if (rx & URXD_BRK) {
866 sport->port.icount.brk++;
867 if (uart_handle_break(&sport->port))
868 continue;
869 }
870 else if (rx & URXD_PRERR)
871 sport->port.icount.parity++;
872 else if (rx & URXD_FRMERR)
873 sport->port.icount.frame++;
874 if (rx & URXD_OVRRUN)
875 sport->port.icount.overrun++;
876
877 if (rx & sport->port.ignore_status_mask)
878 continue;
879
880 rx &= (sport->port.read_status_mask | 0xFF);
881
882 if (rx & URXD_BRK)
883 flg = TTY_BREAK;
884 else if (rx & URXD_PRERR)
885 flg = TTY_PARITY;
886 else if (rx & URXD_FRMERR)
887 flg = TTY_FRAME;
888 if (rx & URXD_OVRRUN)
889 flg = TTY_OVERRUN;
890
891 sport->port.sysrq = 0;
892 } else if (uart_handle_sysrq_char(&sport->port, (unsigned char)rx)) {
893 continue;
894 }
895
896 if (sport->port.ignore_status_mask & URXD_DUMMY_READ)
897 continue;
898
899 if (tty_insert_flip_char(port, rx, flg) == 0)
900 sport->port.icount.buf_overrun++;
901 }
902
903 tty_flip_buffer_push(port);
904
905 return IRQ_HANDLED;
906 }
907
imx_uart_rxint(int irq,void * dev_id)908 static irqreturn_t imx_uart_rxint(int irq, void *dev_id)
909 {
910 struct imx_port *sport = dev_id;
911 irqreturn_t ret;
912
913 spin_lock(&sport->port.lock);
914
915 ret = __imx_uart_rxint(irq, dev_id);
916
917 spin_unlock(&sport->port.lock);
918
919 return ret;
920 }
921
922 static void imx_uart_clear_rx_errors(struct imx_port *sport);
923
924 /*
925 * We have a modem side uart, so the meanings of RTS and CTS are inverted.
926 */
imx_uart_get_hwmctrl(struct imx_port * sport)927 static unsigned int imx_uart_get_hwmctrl(struct imx_port *sport)
928 {
929 unsigned int tmp = TIOCM_DSR;
930 unsigned usr1 = imx_uart_readl(sport, USR1);
931 unsigned usr2 = imx_uart_readl(sport, USR2);
932
933 if (usr1 & USR1_RTSS)
934 tmp |= TIOCM_CTS;
935
936 /* in DCE mode DCDIN is always 0 */
937 if (!(usr2 & USR2_DCDIN))
938 tmp |= TIOCM_CAR;
939
940 if (sport->dte_mode)
941 if (!(imx_uart_readl(sport, USR2) & USR2_RIIN))
942 tmp |= TIOCM_RI;
943
944 return tmp;
945 }
946
947 /*
948 * Handle any change of modem status signal since we were last called.
949 */
imx_uart_mctrl_check(struct imx_port * sport)950 static void imx_uart_mctrl_check(struct imx_port *sport)
951 {
952 unsigned int status, changed;
953
954 status = imx_uart_get_hwmctrl(sport);
955 changed = status ^ sport->old_status;
956
957 if (changed == 0)
958 return;
959
960 sport->old_status = status;
961
962 if (changed & TIOCM_RI && status & TIOCM_RI)
963 sport->port.icount.rng++;
964 if (changed & TIOCM_DSR)
965 sport->port.icount.dsr++;
966 if (changed & TIOCM_CAR)
967 uart_handle_dcd_change(&sport->port, status & TIOCM_CAR);
968 if (changed & TIOCM_CTS)
969 uart_handle_cts_change(&sport->port, status & TIOCM_CTS);
970
971 wake_up_interruptible(&sport->port.state->port.delta_msr_wait);
972 }
973
imx_uart_int(int irq,void * dev_id)974 static irqreturn_t imx_uart_int(int irq, void *dev_id)
975 {
976 struct imx_port *sport = dev_id;
977 unsigned int usr1, usr2, ucr1, ucr2, ucr3, ucr4;
978 irqreturn_t ret = IRQ_NONE;
979
980 spin_lock(&sport->port.lock);
981
982 usr1 = imx_uart_readl(sport, USR1);
983 usr2 = imx_uart_readl(sport, USR2);
984 ucr1 = imx_uart_readl(sport, UCR1);
985 ucr2 = imx_uart_readl(sport, UCR2);
986 ucr3 = imx_uart_readl(sport, UCR3);
987 ucr4 = imx_uart_readl(sport, UCR4);
988
989 /*
990 * Even if a condition is true that can trigger an irq only handle it if
991 * the respective irq source is enabled. This prevents some undesired
992 * actions, for example if a character that sits in the RX FIFO and that
993 * should be fetched via DMA is tried to be fetched using PIO. Or the
994 * receiver is currently off and so reading from URXD0 results in an
995 * exception. So just mask the (raw) status bits for disabled irqs.
996 */
997 if ((ucr1 & UCR1_RRDYEN) == 0)
998 usr1 &= ~USR1_RRDY;
999 if ((ucr2 & UCR2_ATEN) == 0)
1000 usr1 &= ~USR1_AGTIM;
1001 if ((ucr1 & UCR1_TRDYEN) == 0)
1002 usr1 &= ~USR1_TRDY;
1003 if ((ucr4 & UCR4_TCEN) == 0)
1004 usr2 &= ~USR2_TXDC;
1005 if ((ucr3 & UCR3_DTRDEN) == 0)
1006 usr1 &= ~USR1_DTRD;
1007 if ((ucr1 & UCR1_RTSDEN) == 0)
1008 usr1 &= ~USR1_RTSD;
1009 if ((ucr3 & UCR3_AWAKEN) == 0)
1010 usr1 &= ~USR1_AWAKE;
1011 if ((ucr4 & UCR4_OREN) == 0)
1012 usr2 &= ~USR2_ORE;
1013
1014 if (usr1 & (USR1_RRDY | USR1_AGTIM)) {
1015 imx_uart_writel(sport, USR1_AGTIM, USR1);
1016
1017 __imx_uart_rxint(irq, dev_id);
1018 ret = IRQ_HANDLED;
1019 }
1020
1021 if ((usr1 & USR1_TRDY) || (usr2 & USR2_TXDC)) {
1022 imx_uart_transmit_buffer(sport);
1023 ret = IRQ_HANDLED;
1024 }
1025
1026 if (usr1 & USR1_DTRD) {
1027 imx_uart_writel(sport, USR1_DTRD, USR1);
1028
1029 imx_uart_mctrl_check(sport);
1030
1031 ret = IRQ_HANDLED;
1032 }
1033
1034 if (usr1 & USR1_RTSD) {
1035 __imx_uart_rtsint(irq, dev_id);
1036 ret = IRQ_HANDLED;
1037 }
1038
1039 if (usr1 & USR1_AWAKE) {
1040 imx_uart_writel(sport, USR1_AWAKE, USR1);
1041 ret = IRQ_HANDLED;
1042 }
1043
1044 if (usr2 & USR2_ORE) {
1045 sport->port.icount.overrun++;
1046 imx_uart_writel(sport, USR2_ORE, USR2);
1047 ret = IRQ_HANDLED;
1048 }
1049
1050 spin_unlock(&sport->port.lock);
1051
1052 return ret;
1053 }
1054
1055 /*
1056 * Return TIOCSER_TEMT when transmitter is not busy.
1057 */
imx_uart_tx_empty(struct uart_port * port)1058 static unsigned int imx_uart_tx_empty(struct uart_port *port)
1059 {
1060 struct imx_port *sport = (struct imx_port *)port;
1061 unsigned int ret;
1062
1063 ret = (imx_uart_readl(sport, USR2) & USR2_TXDC) ? TIOCSER_TEMT : 0;
1064
1065 /* If the TX DMA is working, return 0. */
1066 if (sport->dma_is_txing)
1067 ret = 0;
1068
1069 return ret;
1070 }
1071
1072 /* called with port.lock taken and irqs off */
imx_uart_get_mctrl(struct uart_port * port)1073 static unsigned int imx_uart_get_mctrl(struct uart_port *port)
1074 {
1075 struct imx_port *sport = (struct imx_port *)port;
1076 unsigned int ret = imx_uart_get_hwmctrl(sport);
1077
1078 mctrl_gpio_get(sport->gpios, &ret);
1079
1080 return ret;
1081 }
1082
1083 /* called with port.lock taken and irqs off */
imx_uart_set_mctrl(struct uart_port * port,unsigned int mctrl)1084 static void imx_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
1085 {
1086 struct imx_port *sport = (struct imx_port *)port;
1087 u32 ucr3, uts;
1088
1089 if (!(port->rs485.flags & SER_RS485_ENABLED)) {
1090 u32 ucr2;
1091
1092 /*
1093 * Turn off autoRTS if RTS is lowered and restore autoRTS
1094 * setting if RTS is raised.
1095 */
1096 ucr2 = imx_uart_readl(sport, UCR2);
1097 ucr2 &= ~(UCR2_CTS | UCR2_CTSC);
1098 if (mctrl & TIOCM_RTS) {
1099 ucr2 |= UCR2_CTS;
1100 /*
1101 * UCR2_IRTS is unset if and only if the port is
1102 * configured for CRTSCTS, so we use inverted UCR2_IRTS
1103 * to get the state to restore to.
1104 */
1105 if (!(ucr2 & UCR2_IRTS))
1106 ucr2 |= UCR2_CTSC;
1107 }
1108 imx_uart_writel(sport, ucr2, UCR2);
1109 }
1110
1111 ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_DSR;
1112 if (!(mctrl & TIOCM_DTR))
1113 ucr3 |= UCR3_DSR;
1114 imx_uart_writel(sport, ucr3, UCR3);
1115
1116 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport)) & ~UTS_LOOP;
1117 if (mctrl & TIOCM_LOOP)
1118 uts |= UTS_LOOP;
1119 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
1120
1121 mctrl_gpio_set(sport->gpios, mctrl);
1122 }
1123
1124 /*
1125 * Interrupts always disabled.
1126 */
imx_uart_break_ctl(struct uart_port * port,int break_state)1127 static void imx_uart_break_ctl(struct uart_port *port, int break_state)
1128 {
1129 struct imx_port *sport = (struct imx_port *)port;
1130 unsigned long flags;
1131 u32 ucr1;
1132
1133 spin_lock_irqsave(&sport->port.lock, flags);
1134
1135 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_SNDBRK;
1136
1137 if (break_state != 0)
1138 ucr1 |= UCR1_SNDBRK;
1139
1140 imx_uart_writel(sport, ucr1, UCR1);
1141
1142 spin_unlock_irqrestore(&sport->port.lock, flags);
1143 }
1144
1145 /*
1146 * This is our per-port timeout handler, for checking the
1147 * modem status signals.
1148 */
imx_uart_timeout(struct timer_list * t)1149 static void imx_uart_timeout(struct timer_list *t)
1150 {
1151 struct imx_port *sport = from_timer(sport, t, timer);
1152 unsigned long flags;
1153
1154 if (sport->port.state) {
1155 spin_lock_irqsave(&sport->port.lock, flags);
1156 imx_uart_mctrl_check(sport);
1157 spin_unlock_irqrestore(&sport->port.lock, flags);
1158
1159 mod_timer(&sport->timer, jiffies + MCTRL_TIMEOUT);
1160 }
1161 }
1162
1163 /*
1164 * There are two kinds of RX DMA interrupts(such as in the MX6Q):
1165 * [1] the RX DMA buffer is full.
1166 * [2] the aging timer expires
1167 *
1168 * Condition [2] is triggered when a character has been sitting in the FIFO
1169 * for at least 8 byte durations.
1170 */
imx_uart_dma_rx_callback(void * data)1171 static void imx_uart_dma_rx_callback(void *data)
1172 {
1173 struct imx_port *sport = data;
1174 struct dma_chan *chan = sport->dma_chan_rx;
1175 struct scatterlist *sgl = &sport->rx_sgl;
1176 struct tty_port *port = &sport->port.state->port;
1177 struct dma_tx_state state;
1178 struct circ_buf *rx_ring = &sport->rx_ring;
1179 enum dma_status status;
1180 unsigned int w_bytes = 0;
1181 unsigned int r_bytes;
1182 unsigned int bd_size;
1183
1184 status = dmaengine_tx_status(chan, sport->rx_cookie, &state);
1185
1186 if (status == DMA_ERROR) {
1187 spin_lock(&sport->port.lock);
1188 imx_uart_clear_rx_errors(sport);
1189 spin_unlock(&sport->port.lock);
1190 return;
1191 }
1192
1193 /*
1194 * The state-residue variable represents the empty space
1195 * relative to the entire buffer. Taking this in consideration
1196 * the head is always calculated base on the buffer total
1197 * length - DMA transaction residue. The UART script from the
1198 * SDMA firmware will jump to the next buffer descriptor,
1199 * once a DMA transaction if finalized (IMX53 RM - A.4.1.2.4).
1200 * Taking this in consideration the tail is always at the
1201 * beginning of the buffer descriptor that contains the head.
1202 */
1203
1204 /* Calculate the head */
1205 rx_ring->head = sg_dma_len(sgl) - state.residue;
1206
1207 /* Calculate the tail. */
1208 bd_size = sg_dma_len(sgl) / sport->rx_periods;
1209 rx_ring->tail = ((rx_ring->head-1) / bd_size) * bd_size;
1210
1211 if (rx_ring->head <= sg_dma_len(sgl) &&
1212 rx_ring->head > rx_ring->tail) {
1213
1214 /* Move data from tail to head */
1215 r_bytes = rx_ring->head - rx_ring->tail;
1216
1217 /* If we received something, check for 0xff flood */
1218 spin_lock(&sport->port.lock);
1219 imx_uart_check_flood(sport, imx_uart_readl(sport, USR2));
1220 spin_unlock(&sport->port.lock);
1221
1222 if (!(sport->port.ignore_status_mask & URXD_DUMMY_READ)) {
1223
1224 /* CPU claims ownership of RX DMA buffer */
1225 dma_sync_sg_for_cpu(sport->port.dev, sgl, 1,
1226 DMA_FROM_DEVICE);
1227
1228 w_bytes = tty_insert_flip_string(port,
1229 sport->rx_buf + rx_ring->tail, r_bytes);
1230
1231 /* UART retrieves ownership of RX DMA buffer */
1232 dma_sync_sg_for_device(sport->port.dev, sgl, 1,
1233 DMA_FROM_DEVICE);
1234
1235 if (w_bytes != r_bytes)
1236 sport->port.icount.buf_overrun++;
1237
1238 sport->port.icount.rx += w_bytes;
1239 }
1240 } else {
1241 WARN_ON(rx_ring->head > sg_dma_len(sgl));
1242 WARN_ON(rx_ring->head <= rx_ring->tail);
1243 }
1244
1245 if (w_bytes) {
1246 tty_flip_buffer_push(port);
1247 dev_dbg(sport->port.dev, "We get %d bytes.\n", w_bytes);
1248 }
1249 }
1250
imx_uart_start_rx_dma(struct imx_port * sport)1251 static int imx_uart_start_rx_dma(struct imx_port *sport)
1252 {
1253 struct scatterlist *sgl = &sport->rx_sgl;
1254 struct dma_chan *chan = sport->dma_chan_rx;
1255 struct device *dev = sport->port.dev;
1256 struct dma_async_tx_descriptor *desc;
1257 int ret;
1258
1259 sport->rx_ring.head = 0;
1260 sport->rx_ring.tail = 0;
1261
1262 sg_init_one(sgl, sport->rx_buf, sport->rx_buf_size);
1263 ret = dma_map_sg(dev, sgl, 1, DMA_FROM_DEVICE);
1264 if (ret == 0) {
1265 dev_err(dev, "DMA mapping error for RX.\n");
1266 return -EINVAL;
1267 }
1268
1269 desc = dmaengine_prep_dma_cyclic(chan, sg_dma_address(sgl),
1270 sg_dma_len(sgl), sg_dma_len(sgl) / sport->rx_periods,
1271 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
1272
1273 if (!desc) {
1274 dma_unmap_sg(dev, sgl, 1, DMA_FROM_DEVICE);
1275 dev_err(dev, "We cannot prepare for the RX slave dma!\n");
1276 return -EINVAL;
1277 }
1278 desc->callback = imx_uart_dma_rx_callback;
1279 desc->callback_param = sport;
1280
1281 dev_dbg(dev, "RX: prepare for the DMA.\n");
1282 sport->dma_is_rxing = 1;
1283 sport->rx_cookie = dmaengine_submit(desc);
1284 dma_async_issue_pending(chan);
1285 return 0;
1286 }
1287
imx_uart_clear_rx_errors(struct imx_port * sport)1288 static void imx_uart_clear_rx_errors(struct imx_port *sport)
1289 {
1290 struct tty_port *port = &sport->port.state->port;
1291 u32 usr1, usr2;
1292
1293 usr1 = imx_uart_readl(sport, USR1);
1294 usr2 = imx_uart_readl(sport, USR2);
1295
1296 if (usr2 & USR2_BRCD) {
1297 sport->port.icount.brk++;
1298 imx_uart_writel(sport, USR2_BRCD, USR2);
1299 uart_handle_break(&sport->port);
1300 if (tty_insert_flip_char(port, 0, TTY_BREAK) == 0)
1301 sport->port.icount.buf_overrun++;
1302 tty_flip_buffer_push(port);
1303 } else {
1304 if (usr1 & USR1_FRAMERR) {
1305 sport->port.icount.frame++;
1306 imx_uart_writel(sport, USR1_FRAMERR, USR1);
1307 } else if (usr1 & USR1_PARITYERR) {
1308 sport->port.icount.parity++;
1309 imx_uart_writel(sport, USR1_PARITYERR, USR1);
1310 }
1311 }
1312
1313 if (usr2 & USR2_ORE) {
1314 sport->port.icount.overrun++;
1315 imx_uart_writel(sport, USR2_ORE, USR2);
1316 }
1317
1318 sport->idle_counter = 0;
1319
1320 }
1321
1322 #define TXTL_DEFAULT 2 /* reset default */
1323 #define RXTL_DEFAULT 8 /* 8 characters or aging timer */
1324 #define TXTL_DMA 8 /* DMA burst setting */
1325 #define RXTL_DMA 9 /* DMA burst setting */
1326
imx_uart_setup_ufcr(struct imx_port * sport,unsigned char txwl,unsigned char rxwl)1327 static void imx_uart_setup_ufcr(struct imx_port *sport,
1328 unsigned char txwl, unsigned char rxwl)
1329 {
1330 unsigned int val;
1331
1332 /* set receiver / transmitter trigger level */
1333 val = imx_uart_readl(sport, UFCR) & (UFCR_RFDIV | UFCR_DCEDTE);
1334 val |= txwl << UFCR_TXTL_SHF | rxwl;
1335 imx_uart_writel(sport, val, UFCR);
1336 }
1337
imx_uart_dma_exit(struct imx_port * sport)1338 static void imx_uart_dma_exit(struct imx_port *sport)
1339 {
1340 if (sport->dma_chan_rx) {
1341 dmaengine_terminate_sync(sport->dma_chan_rx);
1342 dma_release_channel(sport->dma_chan_rx);
1343 sport->dma_chan_rx = NULL;
1344 sport->rx_cookie = -EINVAL;
1345 kfree(sport->rx_buf);
1346 sport->rx_buf = NULL;
1347 }
1348
1349 if (sport->dma_chan_tx) {
1350 dmaengine_terminate_sync(sport->dma_chan_tx);
1351 dma_release_channel(sport->dma_chan_tx);
1352 sport->dma_chan_tx = NULL;
1353 }
1354 }
1355
imx_uart_dma_init(struct imx_port * sport)1356 static int imx_uart_dma_init(struct imx_port *sport)
1357 {
1358 struct dma_slave_config slave_config = {};
1359 struct device *dev = sport->port.dev;
1360 int ret;
1361
1362 /* Prepare for RX : */
1363 sport->dma_chan_rx = dma_request_slave_channel(dev, "rx");
1364 if (!sport->dma_chan_rx) {
1365 dev_dbg(dev, "cannot get the DMA channel.\n");
1366 ret = -EINVAL;
1367 goto err;
1368 }
1369
1370 slave_config.direction = DMA_DEV_TO_MEM;
1371 slave_config.src_addr = sport->port.mapbase + URXD0;
1372 slave_config.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1373 /* one byte less than the watermark level to enable the aging timer */
1374 slave_config.src_maxburst = RXTL_DMA - 1;
1375 ret = dmaengine_slave_config(sport->dma_chan_rx, &slave_config);
1376 if (ret) {
1377 dev_err(dev, "error in RX dma configuration.\n");
1378 goto err;
1379 }
1380
1381 sport->rx_buf_size = sport->rx_period_length * sport->rx_periods;
1382 sport->rx_buf = kzalloc(sport->rx_buf_size, GFP_KERNEL);
1383 if (!sport->rx_buf) {
1384 ret = -ENOMEM;
1385 goto err;
1386 }
1387 sport->rx_ring.buf = sport->rx_buf;
1388
1389 /* Prepare for TX : */
1390 sport->dma_chan_tx = dma_request_slave_channel(dev, "tx");
1391 if (!sport->dma_chan_tx) {
1392 dev_err(dev, "cannot get the TX DMA channel!\n");
1393 ret = -EINVAL;
1394 goto err;
1395 }
1396
1397 slave_config.direction = DMA_MEM_TO_DEV;
1398 slave_config.dst_addr = sport->port.mapbase + URTX0;
1399 slave_config.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
1400 slave_config.dst_maxburst = TXTL_DMA;
1401 ret = dmaengine_slave_config(sport->dma_chan_tx, &slave_config);
1402 if (ret) {
1403 dev_err(dev, "error in TX dma configuration.");
1404 goto err;
1405 }
1406
1407 return 0;
1408 err:
1409 imx_uart_dma_exit(sport);
1410 return ret;
1411 }
1412
imx_uart_enable_dma(struct imx_port * sport)1413 static void imx_uart_enable_dma(struct imx_port *sport)
1414 {
1415 u32 ucr1;
1416
1417 imx_uart_setup_ufcr(sport, TXTL_DMA, RXTL_DMA);
1418
1419 /* set UCR1 */
1420 ucr1 = imx_uart_readl(sport, UCR1);
1421 ucr1 |= UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN;
1422 imx_uart_writel(sport, ucr1, UCR1);
1423
1424 sport->dma_is_enabled = 1;
1425 }
1426
imx_uart_disable_dma(struct imx_port * sport)1427 static void imx_uart_disable_dma(struct imx_port *sport)
1428 {
1429 u32 ucr1;
1430
1431 /* clear UCR1 */
1432 ucr1 = imx_uart_readl(sport, UCR1);
1433 ucr1 &= ~(UCR1_RXDMAEN | UCR1_TXDMAEN | UCR1_ATDMAEN);
1434 imx_uart_writel(sport, ucr1, UCR1);
1435
1436 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1437
1438 sport->dma_is_enabled = 0;
1439 }
1440
1441 /* half the RX buffer size */
1442 #define CTSTL 16
1443
imx_uart_startup(struct uart_port * port)1444 static int imx_uart_startup(struct uart_port *port)
1445 {
1446 struct imx_port *sport = (struct imx_port *)port;
1447 int retval;
1448 unsigned long flags;
1449 int dma_is_inited = 0;
1450 u32 ucr1, ucr2, ucr3, ucr4;
1451
1452 retval = clk_prepare_enable(sport->clk_per);
1453 if (retval)
1454 return retval;
1455 retval = clk_prepare_enable(sport->clk_ipg);
1456 if (retval) {
1457 clk_disable_unprepare(sport->clk_per);
1458 return retval;
1459 }
1460
1461 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1462
1463 /* disable the DREN bit (Data Ready interrupt enable) before
1464 * requesting IRQs
1465 */
1466 ucr4 = imx_uart_readl(sport, UCR4);
1467
1468 /* set the trigger level for CTS */
1469 ucr4 &= ~(UCR4_CTSTL_MASK << UCR4_CTSTL_SHF);
1470 ucr4 |= CTSTL << UCR4_CTSTL_SHF;
1471
1472 imx_uart_writel(sport, ucr4 & ~UCR4_DREN, UCR4);
1473
1474 /* Can we enable the DMA support? */
1475 if (!uart_console(port) && imx_uart_dma_init(sport) == 0)
1476 dma_is_inited = 1;
1477
1478 spin_lock_irqsave(&sport->port.lock, flags);
1479
1480 /* Reset fifo's and state machines */
1481 imx_uart_soft_reset(sport);
1482
1483 /*
1484 * Finally, clear and enable interrupts
1485 */
1486 imx_uart_writel(sport, USR1_RTSD | USR1_DTRD, USR1);
1487 imx_uart_writel(sport, USR2_ORE, USR2);
1488
1489 ucr1 = imx_uart_readl(sport, UCR1) & ~UCR1_RRDYEN;
1490 ucr1 |= UCR1_UARTEN;
1491 if (sport->have_rtscts)
1492 ucr1 |= UCR1_RTSDEN;
1493
1494 imx_uart_writel(sport, ucr1, UCR1);
1495
1496 ucr4 = imx_uart_readl(sport, UCR4) & ~(UCR4_OREN | UCR4_INVR);
1497 if (!dma_is_inited)
1498 ucr4 |= UCR4_OREN;
1499 if (sport->inverted_rx)
1500 ucr4 |= UCR4_INVR;
1501 imx_uart_writel(sport, ucr4, UCR4);
1502
1503 ucr3 = imx_uart_readl(sport, UCR3) & ~UCR3_INVT;
1504 /*
1505 * configure tx polarity before enabling tx
1506 */
1507 if (sport->inverted_tx)
1508 ucr3 |= UCR3_INVT;
1509
1510 if (!imx_uart_is_imx1(sport)) {
1511 ucr3 |= UCR3_DTRDEN | UCR3_RI | UCR3_DCD;
1512
1513 if (sport->dte_mode)
1514 /* disable broken interrupts */
1515 ucr3 &= ~(UCR3_RI | UCR3_DCD);
1516 }
1517 imx_uart_writel(sport, ucr3, UCR3);
1518
1519 ucr2 = imx_uart_readl(sport, UCR2) & ~UCR2_ATEN;
1520 ucr2 |= (UCR2_RXEN | UCR2_TXEN);
1521 if (!sport->have_rtscts)
1522 ucr2 |= UCR2_IRTS;
1523 /*
1524 * make sure the edge sensitive RTS-irq is disabled,
1525 * we're using RTSD instead.
1526 */
1527 if (!imx_uart_is_imx1(sport))
1528 ucr2 &= ~UCR2_RTSEN;
1529 imx_uart_writel(sport, ucr2, UCR2);
1530
1531 /*
1532 * Enable modem status interrupts
1533 */
1534 imx_uart_enable_ms(&sport->port);
1535
1536 if (dma_is_inited) {
1537 imx_uart_enable_dma(sport);
1538 imx_uart_start_rx_dma(sport);
1539 } else {
1540 ucr1 = imx_uart_readl(sport, UCR1);
1541 ucr1 |= UCR1_RRDYEN;
1542 imx_uart_writel(sport, ucr1, UCR1);
1543
1544 ucr2 = imx_uart_readl(sport, UCR2);
1545 ucr2 |= UCR2_ATEN;
1546 imx_uart_writel(sport, ucr2, UCR2);
1547 }
1548
1549 imx_uart_disable_loopback_rs485(sport);
1550
1551 spin_unlock_irqrestore(&sport->port.lock, flags);
1552
1553 return 0;
1554 }
1555
imx_uart_shutdown(struct uart_port * port)1556 static void imx_uart_shutdown(struct uart_port *port)
1557 {
1558 struct imx_port *sport = (struct imx_port *)port;
1559 unsigned long flags;
1560 u32 ucr1, ucr2, ucr4, uts;
1561
1562 if (sport->dma_is_enabled) {
1563 dmaengine_terminate_sync(sport->dma_chan_tx);
1564 if (sport->dma_is_txing) {
1565 dma_unmap_sg(sport->port.dev, &sport->tx_sgl[0],
1566 sport->dma_tx_nents, DMA_TO_DEVICE);
1567 sport->dma_is_txing = 0;
1568 }
1569 dmaengine_terminate_sync(sport->dma_chan_rx);
1570 if (sport->dma_is_rxing) {
1571 dma_unmap_sg(sport->port.dev, &sport->rx_sgl,
1572 1, DMA_FROM_DEVICE);
1573 sport->dma_is_rxing = 0;
1574 }
1575
1576 spin_lock_irqsave(&sport->port.lock, flags);
1577 imx_uart_stop_tx(port);
1578 imx_uart_stop_rx(port);
1579 imx_uart_disable_dma(sport);
1580 spin_unlock_irqrestore(&sport->port.lock, flags);
1581 imx_uart_dma_exit(sport);
1582 }
1583
1584 mctrl_gpio_disable_ms(sport->gpios);
1585
1586 spin_lock_irqsave(&sport->port.lock, flags);
1587 ucr2 = imx_uart_readl(sport, UCR2);
1588 ucr2 &= ~(UCR2_TXEN | UCR2_ATEN);
1589 imx_uart_writel(sport, ucr2, UCR2);
1590 spin_unlock_irqrestore(&sport->port.lock, flags);
1591
1592 /*
1593 * Stop our timer.
1594 */
1595 del_timer_sync(&sport->timer);
1596
1597 /*
1598 * Disable all interrupts, port and break condition.
1599 */
1600
1601 spin_lock_irqsave(&sport->port.lock, flags);
1602
1603 ucr1 = imx_uart_readl(sport, UCR1);
1604 ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN | UCR1_RXDMAEN |
1605 UCR1_ATDMAEN | UCR1_SNDBRK);
1606 /* See SER_RS485_ENABLED/UTS_LOOP comment in imx_uart_probe() */
1607 if (port->rs485.flags & SER_RS485_ENABLED &&
1608 port->rs485.flags & SER_RS485_RTS_ON_SEND &&
1609 sport->have_rtscts && !sport->have_rtsgpio) {
1610 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport));
1611 uts |= UTS_LOOP;
1612 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
1613 ucr1 |= UCR1_UARTEN;
1614 } else {
1615 ucr1 &= ~UCR1_UARTEN;
1616 }
1617 imx_uart_writel(sport, ucr1, UCR1);
1618
1619 ucr4 = imx_uart_readl(sport, UCR4);
1620 ucr4 &= ~UCR4_TCEN;
1621 imx_uart_writel(sport, ucr4, UCR4);
1622
1623 spin_unlock_irqrestore(&sport->port.lock, flags);
1624
1625 clk_disable_unprepare(sport->clk_per);
1626 clk_disable_unprepare(sport->clk_ipg);
1627 }
1628
1629 /* called with port.lock taken and irqs off */
imx_uart_flush_buffer(struct uart_port * port)1630 static void imx_uart_flush_buffer(struct uart_port *port)
1631 {
1632 struct imx_port *sport = (struct imx_port *)port;
1633 struct scatterlist *sgl = &sport->tx_sgl[0];
1634
1635 if (!sport->dma_chan_tx)
1636 return;
1637
1638 sport->tx_bytes = 0;
1639 dmaengine_terminate_all(sport->dma_chan_tx);
1640 if (sport->dma_is_txing) {
1641 u32 ucr1;
1642
1643 dma_unmap_sg(sport->port.dev, sgl, sport->dma_tx_nents,
1644 DMA_TO_DEVICE);
1645 ucr1 = imx_uart_readl(sport, UCR1);
1646 ucr1 &= ~UCR1_TXDMAEN;
1647 imx_uart_writel(sport, ucr1, UCR1);
1648 sport->dma_is_txing = 0;
1649 }
1650
1651 imx_uart_soft_reset(sport);
1652
1653 }
1654
1655 static void
imx_uart_set_termios(struct uart_port * port,struct ktermios * termios,const struct ktermios * old)1656 imx_uart_set_termios(struct uart_port *port, struct ktermios *termios,
1657 const struct ktermios *old)
1658 {
1659 struct imx_port *sport = (struct imx_port *)port;
1660 unsigned long flags;
1661 u32 ucr2, old_ucr2, ufcr;
1662 unsigned int baud, quot;
1663 unsigned int old_csize = old ? old->c_cflag & CSIZE : CS8;
1664 unsigned long div;
1665 unsigned long num, denom, old_ubir, old_ubmr;
1666 uint64_t tdiv64;
1667
1668 /*
1669 * We only support CS7 and CS8.
1670 */
1671 while ((termios->c_cflag & CSIZE) != CS7 &&
1672 (termios->c_cflag & CSIZE) != CS8) {
1673 termios->c_cflag &= ~CSIZE;
1674 termios->c_cflag |= old_csize;
1675 old_csize = CS8;
1676 }
1677
1678 del_timer_sync(&sport->timer);
1679
1680 /*
1681 * Ask the core to calculate the divisor for us.
1682 */
1683 baud = uart_get_baud_rate(port, termios, old, 50, port->uartclk / 16);
1684 quot = uart_get_divisor(port, baud);
1685
1686 spin_lock_irqsave(&sport->port.lock, flags);
1687
1688 /*
1689 * Read current UCR2 and save it for future use, then clear all the bits
1690 * except those we will or may need to preserve.
1691 */
1692 old_ucr2 = imx_uart_readl(sport, UCR2);
1693 ucr2 = old_ucr2 & (UCR2_TXEN | UCR2_RXEN | UCR2_ATEN | UCR2_CTS);
1694
1695 ucr2 |= UCR2_SRST | UCR2_IRTS;
1696 if ((termios->c_cflag & CSIZE) == CS8)
1697 ucr2 |= UCR2_WS;
1698
1699 if (!sport->have_rtscts)
1700 termios->c_cflag &= ~CRTSCTS;
1701
1702 if (port->rs485.flags & SER_RS485_ENABLED) {
1703 /*
1704 * RTS is mandatory for rs485 operation, so keep
1705 * it under manual control and keep transmitter
1706 * disabled.
1707 */
1708 if (port->rs485.flags & SER_RS485_RTS_AFTER_SEND)
1709 imx_uart_rts_active(sport, &ucr2);
1710 else
1711 imx_uart_rts_inactive(sport, &ucr2);
1712
1713 } else if (termios->c_cflag & CRTSCTS) {
1714 /*
1715 * Only let receiver control RTS output if we were not requested
1716 * to have RTS inactive (which then should take precedence).
1717 */
1718 if (ucr2 & UCR2_CTS)
1719 ucr2 |= UCR2_CTSC;
1720 }
1721
1722 if (termios->c_cflag & CRTSCTS)
1723 ucr2 &= ~UCR2_IRTS;
1724 if (termios->c_cflag & CSTOPB)
1725 ucr2 |= UCR2_STPB;
1726 if (termios->c_cflag & PARENB) {
1727 ucr2 |= UCR2_PREN;
1728 if (termios->c_cflag & PARODD)
1729 ucr2 |= UCR2_PROE;
1730 }
1731
1732 sport->port.read_status_mask = 0;
1733 if (termios->c_iflag & INPCK)
1734 sport->port.read_status_mask |= (URXD_FRMERR | URXD_PRERR);
1735 if (termios->c_iflag & (BRKINT | PARMRK))
1736 sport->port.read_status_mask |= URXD_BRK;
1737
1738 /*
1739 * Characters to ignore
1740 */
1741 sport->port.ignore_status_mask = 0;
1742 if (termios->c_iflag & IGNPAR)
1743 sport->port.ignore_status_mask |= URXD_PRERR | URXD_FRMERR;
1744 if (termios->c_iflag & IGNBRK) {
1745 sport->port.ignore_status_mask |= URXD_BRK;
1746 /*
1747 * If we're ignoring parity and break indicators,
1748 * ignore overruns too (for real raw support).
1749 */
1750 if (termios->c_iflag & IGNPAR)
1751 sport->port.ignore_status_mask |= URXD_OVRRUN;
1752 }
1753
1754 if ((termios->c_cflag & CREAD) == 0)
1755 sport->port.ignore_status_mask |= URXD_DUMMY_READ;
1756
1757 /*
1758 * Update the per-port timeout.
1759 */
1760 uart_update_timeout(port, termios->c_cflag, baud);
1761
1762 /* custom-baudrate handling */
1763 div = sport->port.uartclk / (baud * 16);
1764 if (baud == 38400 && quot != div)
1765 baud = sport->port.uartclk / (quot * 16);
1766
1767 div = sport->port.uartclk / (baud * 16);
1768 if (div > 7)
1769 div = 7;
1770 if (!div)
1771 div = 1;
1772
1773 rational_best_approximation(16 * div * baud, sport->port.uartclk,
1774 1 << 16, 1 << 16, &num, &denom);
1775
1776 tdiv64 = sport->port.uartclk;
1777 tdiv64 *= num;
1778 do_div(tdiv64, denom * 16 * div);
1779 tty_termios_encode_baud_rate(termios,
1780 (speed_t)tdiv64, (speed_t)tdiv64);
1781
1782 num -= 1;
1783 denom -= 1;
1784
1785 ufcr = imx_uart_readl(sport, UFCR);
1786 ufcr = (ufcr & (~UFCR_RFDIV)) | UFCR_RFDIV_REG(div);
1787 imx_uart_writel(sport, ufcr, UFCR);
1788
1789 /*
1790 * Two registers below should always be written both and in this
1791 * particular order. One consequence is that we need to check if any of
1792 * them changes and then update both. We do need the check for change
1793 * as even writing the same values seem to "restart"
1794 * transmission/receiving logic in the hardware, that leads to data
1795 * breakage even when rate doesn't in fact change. E.g., user switches
1796 * RTS/CTS handshake and suddenly gets broken bytes.
1797 */
1798 old_ubir = imx_uart_readl(sport, UBIR);
1799 old_ubmr = imx_uart_readl(sport, UBMR);
1800 if (old_ubir != num || old_ubmr != denom) {
1801 imx_uart_writel(sport, num, UBIR);
1802 imx_uart_writel(sport, denom, UBMR);
1803 }
1804
1805 if (!imx_uart_is_imx1(sport))
1806 imx_uart_writel(sport, sport->port.uartclk / div / 1000,
1807 IMX21_ONEMS);
1808
1809 imx_uart_writel(sport, ucr2, UCR2);
1810
1811 if (UART_ENABLE_MS(&sport->port, termios->c_cflag))
1812 imx_uart_enable_ms(&sport->port);
1813
1814 spin_unlock_irqrestore(&sport->port.lock, flags);
1815 }
1816
imx_uart_type(struct uart_port * port)1817 static const char *imx_uart_type(struct uart_port *port)
1818 {
1819 return port->type == PORT_IMX ? "IMX" : NULL;
1820 }
1821
1822 /*
1823 * Configure/autoconfigure the port.
1824 */
imx_uart_config_port(struct uart_port * port,int flags)1825 static void imx_uart_config_port(struct uart_port *port, int flags)
1826 {
1827 if (flags & UART_CONFIG_TYPE)
1828 port->type = PORT_IMX;
1829 }
1830
1831 /*
1832 * Verify the new serial_struct (for TIOCSSERIAL).
1833 * The only change we allow are to the flags and type, and
1834 * even then only between PORT_IMX and PORT_UNKNOWN
1835 */
1836 static int
imx_uart_verify_port(struct uart_port * port,struct serial_struct * ser)1837 imx_uart_verify_port(struct uart_port *port, struct serial_struct *ser)
1838 {
1839 int ret = 0;
1840
1841 if (ser->type != PORT_UNKNOWN && ser->type != PORT_IMX)
1842 ret = -EINVAL;
1843 if (port->irq != ser->irq)
1844 ret = -EINVAL;
1845 if (ser->io_type != UPIO_MEM)
1846 ret = -EINVAL;
1847 if (port->uartclk / 16 != ser->baud_base)
1848 ret = -EINVAL;
1849 if (port->mapbase != (unsigned long)ser->iomem_base)
1850 ret = -EINVAL;
1851 if (port->iobase != ser->port)
1852 ret = -EINVAL;
1853 if (ser->hub6 != 0)
1854 ret = -EINVAL;
1855 return ret;
1856 }
1857
1858 #if defined(CONFIG_CONSOLE_POLL)
1859
imx_uart_poll_init(struct uart_port * port)1860 static int imx_uart_poll_init(struct uart_port *port)
1861 {
1862 struct imx_port *sport = (struct imx_port *)port;
1863 unsigned long flags;
1864 u32 ucr1, ucr2;
1865 int retval;
1866
1867 retval = clk_prepare_enable(sport->clk_ipg);
1868 if (retval)
1869 return retval;
1870 retval = clk_prepare_enable(sport->clk_per);
1871 if (retval)
1872 clk_disable_unprepare(sport->clk_ipg);
1873
1874 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
1875
1876 spin_lock_irqsave(&sport->port.lock, flags);
1877
1878 /*
1879 * Be careful about the order of enabling bits here. First enable the
1880 * receiver (UARTEN + RXEN) and only then the corresponding irqs.
1881 * This prevents that a character that already sits in the RX fifo is
1882 * triggering an irq but the try to fetch it from there results in an
1883 * exception because UARTEN or RXEN is still off.
1884 */
1885 ucr1 = imx_uart_readl(sport, UCR1);
1886 ucr2 = imx_uart_readl(sport, UCR2);
1887
1888 if (imx_uart_is_imx1(sport))
1889 ucr1 |= IMX1_UCR1_UARTCLKEN;
1890
1891 ucr1 |= UCR1_UARTEN;
1892 ucr1 &= ~(UCR1_TRDYEN | UCR1_RTSDEN | UCR1_RRDYEN);
1893
1894 ucr2 |= UCR2_RXEN | UCR2_TXEN;
1895 ucr2 &= ~UCR2_ATEN;
1896
1897 imx_uart_writel(sport, ucr1, UCR1);
1898 imx_uart_writel(sport, ucr2, UCR2);
1899
1900 /* now enable irqs */
1901 imx_uart_writel(sport, ucr1 | UCR1_RRDYEN, UCR1);
1902 imx_uart_writel(sport, ucr2 | UCR2_ATEN, UCR2);
1903
1904 spin_unlock_irqrestore(&sport->port.lock, flags);
1905
1906 return 0;
1907 }
1908
imx_uart_poll_get_char(struct uart_port * port)1909 static int imx_uart_poll_get_char(struct uart_port *port)
1910 {
1911 struct imx_port *sport = (struct imx_port *)port;
1912 if (!(imx_uart_readl(sport, USR2) & USR2_RDR))
1913 return NO_POLL_CHAR;
1914
1915 return imx_uart_readl(sport, URXD0) & URXD_RX_DATA;
1916 }
1917
imx_uart_poll_put_char(struct uart_port * port,unsigned char c)1918 static void imx_uart_poll_put_char(struct uart_port *port, unsigned char c)
1919 {
1920 struct imx_port *sport = (struct imx_port *)port;
1921 unsigned int status;
1922
1923 /* drain */
1924 do {
1925 status = imx_uart_readl(sport, USR1);
1926 } while (~status & USR1_TRDY);
1927
1928 /* write */
1929 imx_uart_writel(sport, c, URTX0);
1930
1931 /* flush */
1932 do {
1933 status = imx_uart_readl(sport, USR2);
1934 } while (~status & USR2_TXDC);
1935 }
1936 #endif
1937
1938 /* called with port.lock taken and irqs off or from .probe without locking */
imx_uart_rs485_config(struct uart_port * port,struct ktermios * termios,struct serial_rs485 * rs485conf)1939 static int imx_uart_rs485_config(struct uart_port *port, struct ktermios *termios,
1940 struct serial_rs485 *rs485conf)
1941 {
1942 struct imx_port *sport = (struct imx_port *)port;
1943 u32 ucr2;
1944
1945 if (rs485conf->flags & SER_RS485_ENABLED) {
1946 /* Enable receiver if low-active RTS signal is requested */
1947 if (sport->have_rtscts && !sport->have_rtsgpio &&
1948 !(rs485conf->flags & SER_RS485_RTS_ON_SEND))
1949 rs485conf->flags |= SER_RS485_RX_DURING_TX;
1950
1951 /* disable transmitter */
1952 ucr2 = imx_uart_readl(sport, UCR2);
1953 if (rs485conf->flags & SER_RS485_RTS_AFTER_SEND)
1954 imx_uart_rts_active(sport, &ucr2);
1955 else
1956 imx_uart_rts_inactive(sport, &ucr2);
1957 imx_uart_writel(sport, ucr2, UCR2);
1958 }
1959
1960 /* Make sure Rx is enabled in case Tx is active with Rx disabled */
1961 if (!(rs485conf->flags & SER_RS485_ENABLED) ||
1962 rs485conf->flags & SER_RS485_RX_DURING_TX)
1963 imx_uart_start_rx(port);
1964
1965 return 0;
1966 }
1967
1968 static const struct uart_ops imx_uart_pops = {
1969 .tx_empty = imx_uart_tx_empty,
1970 .set_mctrl = imx_uart_set_mctrl,
1971 .get_mctrl = imx_uart_get_mctrl,
1972 .stop_tx = imx_uart_stop_tx,
1973 .start_tx = imx_uart_start_tx,
1974 .stop_rx = imx_uart_stop_rx,
1975 .enable_ms = imx_uart_enable_ms,
1976 .break_ctl = imx_uart_break_ctl,
1977 .startup = imx_uart_startup,
1978 .shutdown = imx_uart_shutdown,
1979 .flush_buffer = imx_uart_flush_buffer,
1980 .set_termios = imx_uart_set_termios,
1981 .type = imx_uart_type,
1982 .config_port = imx_uart_config_port,
1983 .verify_port = imx_uart_verify_port,
1984 #if defined(CONFIG_CONSOLE_POLL)
1985 .poll_init = imx_uart_poll_init,
1986 .poll_get_char = imx_uart_poll_get_char,
1987 .poll_put_char = imx_uart_poll_put_char,
1988 #endif
1989 };
1990
1991 static struct imx_port *imx_uart_ports[UART_NR];
1992
1993 #if IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE)
imx_uart_console_putchar(struct uart_port * port,unsigned char ch)1994 static void imx_uart_console_putchar(struct uart_port *port, unsigned char ch)
1995 {
1996 struct imx_port *sport = (struct imx_port *)port;
1997
1998 while (imx_uart_readl(sport, imx_uart_uts_reg(sport)) & UTS_TXFULL)
1999 barrier();
2000
2001 imx_uart_writel(sport, ch, URTX0);
2002 }
2003
2004 /*
2005 * Interrupts are disabled on entering
2006 */
2007 static void
imx_uart_console_write(struct console * co,const char * s,unsigned int count)2008 imx_uart_console_write(struct console *co, const char *s, unsigned int count)
2009 {
2010 struct imx_port *sport = imx_uart_ports[co->index];
2011 struct imx_port_ucrs old_ucr;
2012 unsigned long flags;
2013 unsigned int ucr1, usr2;
2014 int locked = 1;
2015
2016 if (sport->port.sysrq)
2017 locked = 0;
2018 else if (oops_in_progress)
2019 locked = spin_trylock_irqsave(&sport->port.lock, flags);
2020 else
2021 spin_lock_irqsave(&sport->port.lock, flags);
2022
2023 /*
2024 * First, save UCR1/2/3 and then disable interrupts
2025 */
2026 imx_uart_ucrs_save(sport, &old_ucr);
2027 ucr1 = old_ucr.ucr1;
2028
2029 if (imx_uart_is_imx1(sport))
2030 ucr1 |= IMX1_UCR1_UARTCLKEN;
2031 ucr1 |= UCR1_UARTEN;
2032 ucr1 &= ~(UCR1_TRDYEN | UCR1_RRDYEN | UCR1_RTSDEN);
2033
2034 imx_uart_writel(sport, ucr1, UCR1);
2035
2036 imx_uart_writel(sport, old_ucr.ucr2 | UCR2_TXEN, UCR2);
2037
2038 uart_console_write(&sport->port, s, count, imx_uart_console_putchar);
2039
2040 /*
2041 * Finally, wait for transmitter to become empty
2042 * and restore UCR1/2/3
2043 */
2044 read_poll_timeout_atomic(imx_uart_readl, usr2, usr2 & USR2_TXDC,
2045 0, USEC_PER_SEC, false, sport, USR2);
2046 imx_uart_ucrs_restore(sport, &old_ucr);
2047
2048 if (locked)
2049 spin_unlock_irqrestore(&sport->port.lock, flags);
2050 }
2051
2052 /*
2053 * If the port was already initialised (eg, by a boot loader),
2054 * try to determine the current setup.
2055 */
2056 static void
imx_uart_console_get_options(struct imx_port * sport,int * baud,int * parity,int * bits)2057 imx_uart_console_get_options(struct imx_port *sport, int *baud,
2058 int *parity, int *bits)
2059 {
2060
2061 if (imx_uart_readl(sport, UCR1) & UCR1_UARTEN) {
2062 /* ok, the port was enabled */
2063 unsigned int ucr2, ubir, ubmr, uartclk;
2064 unsigned int baud_raw;
2065 unsigned int ucfr_rfdiv;
2066
2067 ucr2 = imx_uart_readl(sport, UCR2);
2068
2069 *parity = 'n';
2070 if (ucr2 & UCR2_PREN) {
2071 if (ucr2 & UCR2_PROE)
2072 *parity = 'o';
2073 else
2074 *parity = 'e';
2075 }
2076
2077 if (ucr2 & UCR2_WS)
2078 *bits = 8;
2079 else
2080 *bits = 7;
2081
2082 ubir = imx_uart_readl(sport, UBIR) & 0xffff;
2083 ubmr = imx_uart_readl(sport, UBMR) & 0xffff;
2084
2085 ucfr_rfdiv = (imx_uart_readl(sport, UFCR) & UFCR_RFDIV) >> 7;
2086 if (ucfr_rfdiv == 6)
2087 ucfr_rfdiv = 7;
2088 else
2089 ucfr_rfdiv = 6 - ucfr_rfdiv;
2090
2091 uartclk = clk_get_rate(sport->clk_per);
2092 uartclk /= ucfr_rfdiv;
2093
2094 { /*
2095 * The next code provides exact computation of
2096 * baud_raw = round(((uartclk/16) * (ubir + 1)) / (ubmr + 1))
2097 * without need of float support or long long division,
2098 * which would be required to prevent 32bit arithmetic overflow
2099 */
2100 unsigned int mul = ubir + 1;
2101 unsigned int div = 16 * (ubmr + 1);
2102 unsigned int rem = uartclk % div;
2103
2104 baud_raw = (uartclk / div) * mul;
2105 baud_raw += (rem * mul + div / 2) / div;
2106 *baud = (baud_raw + 50) / 100 * 100;
2107 }
2108
2109 if (*baud != baud_raw)
2110 dev_info(sport->port.dev, "Console IMX rounded baud rate from %d to %d\n",
2111 baud_raw, *baud);
2112 }
2113 }
2114
2115 static int
imx_uart_console_setup(struct console * co,char * options)2116 imx_uart_console_setup(struct console *co, char *options)
2117 {
2118 struct imx_port *sport;
2119 int baud = 9600;
2120 int bits = 8;
2121 int parity = 'n';
2122 int flow = 'n';
2123 int retval;
2124
2125 /*
2126 * Check whether an invalid uart number has been specified, and
2127 * if so, search for the first available port that does have
2128 * console support.
2129 */
2130 if (co->index == -1 || co->index >= ARRAY_SIZE(imx_uart_ports))
2131 co->index = 0;
2132 sport = imx_uart_ports[co->index];
2133 if (sport == NULL)
2134 return -ENODEV;
2135
2136 /* For setting the registers, we only need to enable the ipg clock. */
2137 retval = clk_prepare_enable(sport->clk_ipg);
2138 if (retval)
2139 goto error_console;
2140
2141 if (options)
2142 uart_parse_options(options, &baud, &parity, &bits, &flow);
2143 else
2144 imx_uart_console_get_options(sport, &baud, &parity, &bits);
2145
2146 imx_uart_setup_ufcr(sport, TXTL_DEFAULT, RXTL_DEFAULT);
2147
2148 retval = uart_set_options(&sport->port, co, baud, parity, bits, flow);
2149
2150 if (retval) {
2151 clk_disable_unprepare(sport->clk_ipg);
2152 goto error_console;
2153 }
2154
2155 retval = clk_prepare_enable(sport->clk_per);
2156 if (retval)
2157 clk_disable_unprepare(sport->clk_ipg);
2158
2159 error_console:
2160 return retval;
2161 }
2162
2163 static int
imx_uart_console_exit(struct console * co)2164 imx_uart_console_exit(struct console *co)
2165 {
2166 struct imx_port *sport = imx_uart_ports[co->index];
2167
2168 clk_disable_unprepare(sport->clk_per);
2169 clk_disable_unprepare(sport->clk_ipg);
2170
2171 return 0;
2172 }
2173
2174 static struct uart_driver imx_uart_uart_driver;
2175 static struct console imx_uart_console = {
2176 .name = DEV_NAME,
2177 .write = imx_uart_console_write,
2178 .device = uart_console_device,
2179 .setup = imx_uart_console_setup,
2180 .exit = imx_uart_console_exit,
2181 .flags = CON_PRINTBUFFER,
2182 .index = -1,
2183 .data = &imx_uart_uart_driver,
2184 };
2185
2186 #define IMX_CONSOLE &imx_uart_console
2187
2188 #else
2189 #define IMX_CONSOLE NULL
2190 #endif
2191
2192 static struct uart_driver imx_uart_uart_driver = {
2193 .owner = THIS_MODULE,
2194 .driver_name = DRIVER_NAME,
2195 .dev_name = DEV_NAME,
2196 .major = SERIAL_IMX_MAJOR,
2197 .minor = MINOR_START,
2198 .nr = ARRAY_SIZE(imx_uart_ports),
2199 .cons = IMX_CONSOLE,
2200 };
2201
imx_trigger_start_tx(struct hrtimer * t)2202 static enum hrtimer_restart imx_trigger_start_tx(struct hrtimer *t)
2203 {
2204 struct imx_port *sport = container_of(t, struct imx_port, trigger_start_tx);
2205 unsigned long flags;
2206
2207 spin_lock_irqsave(&sport->port.lock, flags);
2208 if (sport->tx_state == WAIT_AFTER_RTS)
2209 imx_uart_start_tx(&sport->port);
2210 spin_unlock_irqrestore(&sport->port.lock, flags);
2211
2212 return HRTIMER_NORESTART;
2213 }
2214
imx_trigger_stop_tx(struct hrtimer * t)2215 static enum hrtimer_restart imx_trigger_stop_tx(struct hrtimer *t)
2216 {
2217 struct imx_port *sport = container_of(t, struct imx_port, trigger_stop_tx);
2218 unsigned long flags;
2219
2220 spin_lock_irqsave(&sport->port.lock, flags);
2221 if (sport->tx_state == WAIT_AFTER_SEND)
2222 imx_uart_stop_tx(&sport->port);
2223 spin_unlock_irqrestore(&sport->port.lock, flags);
2224
2225 return HRTIMER_NORESTART;
2226 }
2227
2228 static const struct serial_rs485 imx_rs485_supported = {
2229 .flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND | SER_RS485_RTS_AFTER_SEND |
2230 SER_RS485_RX_DURING_TX,
2231 .delay_rts_before_send = 1,
2232 .delay_rts_after_send = 1,
2233 };
2234
2235 /* Default RX DMA buffer configuration */
2236 #define RX_DMA_PERIODS 16
2237 #define RX_DMA_PERIOD_LEN (PAGE_SIZE / 4)
2238
imx_uart_probe(struct platform_device * pdev)2239 static int imx_uart_probe(struct platform_device *pdev)
2240 {
2241 struct device_node *np = pdev->dev.of_node;
2242 struct imx_port *sport;
2243 void __iomem *base;
2244 u32 dma_buf_conf[2];
2245 int ret = 0;
2246 u32 ucr1, ucr2, uts;
2247 struct resource *res;
2248 int txirq, rxirq, rtsirq;
2249
2250 sport = devm_kzalloc(&pdev->dev, sizeof(*sport), GFP_KERNEL);
2251 if (!sport)
2252 return -ENOMEM;
2253
2254 sport->devdata = of_device_get_match_data(&pdev->dev);
2255
2256 ret = of_alias_get_id(np, "serial");
2257 if (ret < 0) {
2258 dev_err(&pdev->dev, "failed to get alias id, errno %d\n", ret);
2259 return ret;
2260 }
2261 sport->port.line = ret;
2262
2263 sport->have_rtscts = of_property_read_bool(np, "uart-has-rtscts") ||
2264 of_property_read_bool(np, "fsl,uart-has-rtscts"); /* deprecated */
2265
2266 sport->dte_mode = of_property_read_bool(np, "fsl,dte-mode");
2267
2268 sport->have_rtsgpio = of_property_present(np, "rts-gpios");
2269
2270 sport->inverted_tx = of_property_read_bool(np, "fsl,inverted-tx");
2271
2272 sport->inverted_rx = of_property_read_bool(np, "fsl,inverted-rx");
2273
2274 if (!of_property_read_u32_array(np, "fsl,dma-info", dma_buf_conf, 2)) {
2275 sport->rx_period_length = dma_buf_conf[0];
2276 sport->rx_periods = dma_buf_conf[1];
2277 } else {
2278 sport->rx_period_length = RX_DMA_PERIOD_LEN;
2279 sport->rx_periods = RX_DMA_PERIODS;
2280 }
2281
2282 if (sport->port.line >= ARRAY_SIZE(imx_uart_ports)) {
2283 dev_err(&pdev->dev, "serial%d out of range\n",
2284 sport->port.line);
2285 return -EINVAL;
2286 }
2287
2288 base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);
2289 if (IS_ERR(base))
2290 return PTR_ERR(base);
2291
2292 rxirq = platform_get_irq(pdev, 0);
2293 if (rxirq < 0)
2294 return rxirq;
2295 txirq = platform_get_irq_optional(pdev, 1);
2296 rtsirq = platform_get_irq_optional(pdev, 2);
2297
2298 sport->port.dev = &pdev->dev;
2299 sport->port.mapbase = res->start;
2300 sport->port.membase = base;
2301 sport->port.type = PORT_IMX;
2302 sport->port.iotype = UPIO_MEM;
2303 sport->port.irq = rxirq;
2304 sport->port.fifosize = 32;
2305 sport->port.has_sysrq = IS_ENABLED(CONFIG_SERIAL_IMX_CONSOLE);
2306 sport->port.ops = &imx_uart_pops;
2307 sport->port.rs485_config = imx_uart_rs485_config;
2308 /* RTS is required to control the RS485 transmitter */
2309 if (sport->have_rtscts || sport->have_rtsgpio)
2310 sport->port.rs485_supported = imx_rs485_supported;
2311 sport->port.flags = UPF_BOOT_AUTOCONF;
2312 timer_setup(&sport->timer, imx_uart_timeout, 0);
2313
2314 sport->gpios = mctrl_gpio_init(&sport->port, 0);
2315 if (IS_ERR(sport->gpios))
2316 return PTR_ERR(sport->gpios);
2317
2318 sport->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
2319 if (IS_ERR(sport->clk_ipg)) {
2320 ret = PTR_ERR(sport->clk_ipg);
2321 dev_err(&pdev->dev, "failed to get ipg clk: %d\n", ret);
2322 return ret;
2323 }
2324
2325 sport->clk_per = devm_clk_get(&pdev->dev, "per");
2326 if (IS_ERR(sport->clk_per)) {
2327 ret = PTR_ERR(sport->clk_per);
2328 dev_err(&pdev->dev, "failed to get per clk: %d\n", ret);
2329 return ret;
2330 }
2331
2332 sport->port.uartclk = clk_get_rate(sport->clk_per);
2333
2334 /* For register access, we only need to enable the ipg clock. */
2335 ret = clk_prepare_enable(sport->clk_ipg);
2336 if (ret) {
2337 dev_err(&pdev->dev, "failed to enable ipg clk: %d\n", ret);
2338 return ret;
2339 }
2340
2341 ret = uart_get_rs485_mode(&sport->port);
2342 if (ret)
2343 goto err_clk;
2344
2345 /*
2346 * If using the i.MX UART RTS/CTS control then the RTS (CTS_B)
2347 * signal cannot be set low during transmission in case the
2348 * receiver is off (limitation of the i.MX UART IP).
2349 */
2350 if (sport->port.rs485.flags & SER_RS485_ENABLED &&
2351 sport->have_rtscts && !sport->have_rtsgpio &&
2352 (!(sport->port.rs485.flags & SER_RS485_RTS_ON_SEND) &&
2353 !(sport->port.rs485.flags & SER_RS485_RX_DURING_TX)))
2354 dev_err(&pdev->dev,
2355 "low-active RTS not possible when receiver is off, enabling receiver\n");
2356
2357 /* Disable interrupts before requesting them */
2358 ucr1 = imx_uart_readl(sport, UCR1);
2359 ucr1 &= ~(UCR1_ADEN | UCR1_TRDYEN | UCR1_IDEN | UCR1_RRDYEN | UCR1_RTSDEN);
2360 imx_uart_writel(sport, ucr1, UCR1);
2361
2362 /* Disable Ageing Timer interrupt */
2363 ucr2 = imx_uart_readl(sport, UCR2);
2364 ucr2 &= ~UCR2_ATEN;
2365 imx_uart_writel(sport, ucr2, UCR2);
2366
2367 /*
2368 * In case RS485 is enabled without GPIO RTS control, the UART IP
2369 * is used to control CTS signal. Keep both the UART and Receiver
2370 * enabled, otherwise the UART IP pulls CTS signal always HIGH no
2371 * matter how the UCR2 CTSC and CTS bits are set. To prevent any
2372 * data from being fed into the RX FIFO, enable loopback mode in
2373 * UTS register, which disconnects the RX path from external RXD
2374 * pin and connects it to the Transceiver, which is disabled, so
2375 * no data can be fed to the RX FIFO that way.
2376 */
2377 if (sport->port.rs485.flags & SER_RS485_ENABLED &&
2378 sport->have_rtscts && !sport->have_rtsgpio) {
2379 uts = imx_uart_readl(sport, imx_uart_uts_reg(sport));
2380 uts |= UTS_LOOP;
2381 imx_uart_writel(sport, uts, imx_uart_uts_reg(sport));
2382
2383 ucr1 = imx_uart_readl(sport, UCR1);
2384 ucr1 |= UCR1_UARTEN;
2385 imx_uart_writel(sport, ucr1, UCR1);
2386
2387 ucr2 = imx_uart_readl(sport, UCR2);
2388 ucr2 |= UCR2_RXEN;
2389 imx_uart_writel(sport, ucr2, UCR2);
2390 }
2391
2392 if (!imx_uart_is_imx1(sport) && sport->dte_mode) {
2393 /*
2394 * The DCEDTE bit changes the direction of DSR, DCD, DTR and RI
2395 * and influences if UCR3_RI and UCR3_DCD changes the level of RI
2396 * and DCD (when they are outputs) or enables the respective
2397 * irqs. So set this bit early, i.e. before requesting irqs.
2398 */
2399 u32 ufcr = imx_uart_readl(sport, UFCR);
2400 if (!(ufcr & UFCR_DCEDTE))
2401 imx_uart_writel(sport, ufcr | UFCR_DCEDTE, UFCR);
2402
2403 /*
2404 * Disable UCR3_RI and UCR3_DCD irqs. They are also not
2405 * enabled later because they cannot be cleared
2406 * (confirmed on i.MX25) which makes them unusable.
2407 */
2408 imx_uart_writel(sport,
2409 IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP | UCR3_DSR,
2410 UCR3);
2411
2412 } else {
2413 u32 ucr3 = UCR3_DSR;
2414 u32 ufcr = imx_uart_readl(sport, UFCR);
2415 if (ufcr & UFCR_DCEDTE)
2416 imx_uart_writel(sport, ufcr & ~UFCR_DCEDTE, UFCR);
2417
2418 if (!imx_uart_is_imx1(sport))
2419 ucr3 |= IMX21_UCR3_RXDMUXSEL | UCR3_ADNIMP;
2420 imx_uart_writel(sport, ucr3, UCR3);
2421 }
2422
2423 hrtimer_init(&sport->trigger_start_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
2424 hrtimer_init(&sport->trigger_stop_tx, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
2425 sport->trigger_start_tx.function = imx_trigger_start_tx;
2426 sport->trigger_stop_tx.function = imx_trigger_stop_tx;
2427
2428 /*
2429 * Allocate the IRQ(s) i.MX1 has three interrupts whereas later
2430 * chips only have one interrupt.
2431 */
2432 if (txirq > 0) {
2433 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_rxint, 0,
2434 dev_name(&pdev->dev), sport);
2435 if (ret) {
2436 dev_err(&pdev->dev, "failed to request rx irq: %d\n",
2437 ret);
2438 goto err_clk;
2439 }
2440
2441 ret = devm_request_irq(&pdev->dev, txirq, imx_uart_txint, 0,
2442 dev_name(&pdev->dev), sport);
2443 if (ret) {
2444 dev_err(&pdev->dev, "failed to request tx irq: %d\n",
2445 ret);
2446 goto err_clk;
2447 }
2448
2449 ret = devm_request_irq(&pdev->dev, rtsirq, imx_uart_rtsint, 0,
2450 dev_name(&pdev->dev), sport);
2451 if (ret) {
2452 dev_err(&pdev->dev, "failed to request rts irq: %d\n",
2453 ret);
2454 goto err_clk;
2455 }
2456 } else {
2457 ret = devm_request_irq(&pdev->dev, rxirq, imx_uart_int, 0,
2458 dev_name(&pdev->dev), sport);
2459 if (ret) {
2460 dev_err(&pdev->dev, "failed to request irq: %d\n", ret);
2461 goto err_clk;
2462 }
2463 }
2464
2465 imx_uart_ports[sport->port.line] = sport;
2466
2467 platform_set_drvdata(pdev, sport);
2468
2469 ret = uart_add_one_port(&imx_uart_uart_driver, &sport->port);
2470
2471 err_clk:
2472 clk_disable_unprepare(sport->clk_ipg);
2473
2474 return ret;
2475 }
2476
imx_uart_remove(struct platform_device * pdev)2477 static int imx_uart_remove(struct platform_device *pdev)
2478 {
2479 struct imx_port *sport = platform_get_drvdata(pdev);
2480
2481 uart_remove_one_port(&imx_uart_uart_driver, &sport->port);
2482
2483 return 0;
2484 }
2485
imx_uart_restore_context(struct imx_port * sport)2486 static void imx_uart_restore_context(struct imx_port *sport)
2487 {
2488 unsigned long flags;
2489
2490 spin_lock_irqsave(&sport->port.lock, flags);
2491 if (!sport->context_saved) {
2492 spin_unlock_irqrestore(&sport->port.lock, flags);
2493 return;
2494 }
2495
2496 imx_uart_writel(sport, sport->saved_reg[4], UFCR);
2497 imx_uart_writel(sport, sport->saved_reg[5], UESC);
2498 imx_uart_writel(sport, sport->saved_reg[6], UTIM);
2499 imx_uart_writel(sport, sport->saved_reg[7], UBIR);
2500 imx_uart_writel(sport, sport->saved_reg[8], UBMR);
2501 imx_uart_writel(sport, sport->saved_reg[9], IMX21_UTS);
2502 imx_uart_writel(sport, sport->saved_reg[0], UCR1);
2503 imx_uart_writel(sport, sport->saved_reg[1] | UCR2_SRST, UCR2);
2504 imx_uart_writel(sport, sport->saved_reg[2], UCR3);
2505 imx_uart_writel(sport, sport->saved_reg[3], UCR4);
2506 sport->context_saved = false;
2507 spin_unlock_irqrestore(&sport->port.lock, flags);
2508 }
2509
imx_uart_save_context(struct imx_port * sport)2510 static void imx_uart_save_context(struct imx_port *sport)
2511 {
2512 unsigned long flags;
2513
2514 /* Save necessary regs */
2515 spin_lock_irqsave(&sport->port.lock, flags);
2516 sport->saved_reg[0] = imx_uart_readl(sport, UCR1);
2517 sport->saved_reg[1] = imx_uart_readl(sport, UCR2);
2518 sport->saved_reg[2] = imx_uart_readl(sport, UCR3);
2519 sport->saved_reg[3] = imx_uart_readl(sport, UCR4);
2520 sport->saved_reg[4] = imx_uart_readl(sport, UFCR);
2521 sport->saved_reg[5] = imx_uart_readl(sport, UESC);
2522 sport->saved_reg[6] = imx_uart_readl(sport, UTIM);
2523 sport->saved_reg[7] = imx_uart_readl(sport, UBIR);
2524 sport->saved_reg[8] = imx_uart_readl(sport, UBMR);
2525 sport->saved_reg[9] = imx_uart_readl(sport, IMX21_UTS);
2526 sport->context_saved = true;
2527 spin_unlock_irqrestore(&sport->port.lock, flags);
2528 }
2529
imx_uart_enable_wakeup(struct imx_port * sport,bool on)2530 static void imx_uart_enable_wakeup(struct imx_port *sport, bool on)
2531 {
2532 u32 ucr3;
2533
2534 ucr3 = imx_uart_readl(sport, UCR3);
2535 if (on) {
2536 imx_uart_writel(sport, USR1_AWAKE, USR1);
2537 ucr3 |= UCR3_AWAKEN;
2538 } else {
2539 ucr3 &= ~UCR3_AWAKEN;
2540 }
2541 imx_uart_writel(sport, ucr3, UCR3);
2542
2543 if (sport->have_rtscts) {
2544 u32 ucr1 = imx_uart_readl(sport, UCR1);
2545 if (on) {
2546 imx_uart_writel(sport, USR1_RTSD, USR1);
2547 ucr1 |= UCR1_RTSDEN;
2548 } else {
2549 ucr1 &= ~UCR1_RTSDEN;
2550 }
2551 imx_uart_writel(sport, ucr1, UCR1);
2552 }
2553 }
2554
imx_uart_suspend_noirq(struct device * dev)2555 static int imx_uart_suspend_noirq(struct device *dev)
2556 {
2557 struct imx_port *sport = dev_get_drvdata(dev);
2558
2559 imx_uart_save_context(sport);
2560
2561 clk_disable(sport->clk_ipg);
2562
2563 pinctrl_pm_select_sleep_state(dev);
2564
2565 return 0;
2566 }
2567
imx_uart_resume_noirq(struct device * dev)2568 static int imx_uart_resume_noirq(struct device *dev)
2569 {
2570 struct imx_port *sport = dev_get_drvdata(dev);
2571 int ret;
2572
2573 pinctrl_pm_select_default_state(dev);
2574
2575 ret = clk_enable(sport->clk_ipg);
2576 if (ret)
2577 return ret;
2578
2579 imx_uart_restore_context(sport);
2580
2581 return 0;
2582 }
2583
imx_uart_suspend(struct device * dev)2584 static int imx_uart_suspend(struct device *dev)
2585 {
2586 struct imx_port *sport = dev_get_drvdata(dev);
2587 int ret;
2588
2589 uart_suspend_port(&imx_uart_uart_driver, &sport->port);
2590 disable_irq(sport->port.irq);
2591
2592 ret = clk_prepare_enable(sport->clk_ipg);
2593 if (ret)
2594 return ret;
2595
2596 /* enable wakeup from i.MX UART */
2597 imx_uart_enable_wakeup(sport, true);
2598
2599 return 0;
2600 }
2601
imx_uart_resume(struct device * dev)2602 static int imx_uart_resume(struct device *dev)
2603 {
2604 struct imx_port *sport = dev_get_drvdata(dev);
2605
2606 /* disable wakeup from i.MX UART */
2607 imx_uart_enable_wakeup(sport, false);
2608
2609 uart_resume_port(&imx_uart_uart_driver, &sport->port);
2610 enable_irq(sport->port.irq);
2611
2612 clk_disable_unprepare(sport->clk_ipg);
2613
2614 return 0;
2615 }
2616
imx_uart_freeze(struct device * dev)2617 static int imx_uart_freeze(struct device *dev)
2618 {
2619 struct imx_port *sport = dev_get_drvdata(dev);
2620
2621 uart_suspend_port(&imx_uart_uart_driver, &sport->port);
2622
2623 return clk_prepare_enable(sport->clk_ipg);
2624 }
2625
imx_uart_thaw(struct device * dev)2626 static int imx_uart_thaw(struct device *dev)
2627 {
2628 struct imx_port *sport = dev_get_drvdata(dev);
2629
2630 uart_resume_port(&imx_uart_uart_driver, &sport->port);
2631
2632 clk_disable_unprepare(sport->clk_ipg);
2633
2634 return 0;
2635 }
2636
2637 static const struct dev_pm_ops imx_uart_pm_ops = {
2638 .suspend_noirq = imx_uart_suspend_noirq,
2639 .resume_noirq = imx_uart_resume_noirq,
2640 .freeze_noirq = imx_uart_suspend_noirq,
2641 .thaw_noirq = imx_uart_resume_noirq,
2642 .restore_noirq = imx_uart_resume_noirq,
2643 .suspend = imx_uart_suspend,
2644 .resume = imx_uart_resume,
2645 .freeze = imx_uart_freeze,
2646 .thaw = imx_uart_thaw,
2647 .restore = imx_uart_thaw,
2648 };
2649
2650 static struct platform_driver imx_uart_platform_driver = {
2651 .probe = imx_uart_probe,
2652 .remove = imx_uart_remove,
2653
2654 .driver = {
2655 .name = "imx-uart",
2656 .of_match_table = imx_uart_dt_ids,
2657 .pm = &imx_uart_pm_ops,
2658 },
2659 };
2660
imx_uart_init(void)2661 static int __init imx_uart_init(void)
2662 {
2663 int ret = uart_register_driver(&imx_uart_uart_driver);
2664
2665 if (ret)
2666 return ret;
2667
2668 ret = platform_driver_register(&imx_uart_platform_driver);
2669 if (ret != 0)
2670 uart_unregister_driver(&imx_uart_uart_driver);
2671
2672 return ret;
2673 }
2674
imx_uart_exit(void)2675 static void __exit imx_uart_exit(void)
2676 {
2677 platform_driver_unregister(&imx_uart_platform_driver);
2678 uart_unregister_driver(&imx_uart_uart_driver);
2679 }
2680
2681 module_init(imx_uart_init);
2682 module_exit(imx_uart_exit);
2683
2684 MODULE_AUTHOR("Sascha Hauer");
2685 MODULE_DESCRIPTION("IMX generic serial port driver");
2686 MODULE_LICENSE("GPL");
2687 MODULE_ALIAS("platform:imx-uart");
2688