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Searched refs:UART_RSA_BASE (Results 1 – 3 of 3) sorted by relevance

/openbmc/u-boot/include/linux/
H A Dserial_reg.h298 #define UART_RSA_BASE (-8) macro
300 #define UART_RSA_MSR ((UART_RSA_BASE) + 0) /* I/O: Mode Select Register */
307 #define UART_RSA_IER ((UART_RSA_BASE) + 1) /* I/O: Interrupt Enable Register */
315 #define UART_RSA_SRR ((UART_RSA_BASE) + 2) /* IN: Status Read Register */
326 #define UART_RSA_FRR ((UART_RSA_BASE) + 2) /* OUT: FIFO Reset Register */
328 #define UART_RSA_TIVSR ((UART_RSA_BASE) + 3) /* I/O: Timer Interval Value Set Register */
330 #define UART_RSA_TCR ((UART_RSA_BASE) + 4) /* OUT: Timer Control Register */
/openbmc/linux/include/uapi/linux/
H A Dserial_reg.h295 #define UART_RSA_BASE (-8) macro
297 #define UART_RSA_MSR ((UART_RSA_BASE) + 0) /* I/O: Mode Select Register */
304 #define UART_RSA_IER ((UART_RSA_BASE) + 1) /* I/O: Interrupt Enable Register */
312 #define UART_RSA_SRR ((UART_RSA_BASE) + 2) /* IN: Status Read Register */
323 #define UART_RSA_FRR ((UART_RSA_BASE) + 2) /* OUT: FIFO Reset Register */
325 #define UART_RSA_TIVSR ((UART_RSA_BASE) + 3) /* I/O: Timer Interval Value Set Register */
327 #define UART_RSA_TCR ((UART_RSA_BASE) + 4) /* OUT: Timer Control Register */
/openbmc/linux/drivers/tty/serial/8250/
H A D8250_core.c350 unsigned long start = UART_RSA_BASE << up->port.regshift; in serial8250_request_rsa_resource()
371 unsigned long offset = UART_RSA_BASE << up->port.regshift; in serial8250_release_rsa_resource()