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Searched refs:UARTDM_CR (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/drivers/serial/
H A Dserial_msm.c38 #define UARTDM_CR 0xA8 /* Command register */ macro
75 writel(UARTDM_CR_CMD_RESET_ERR, priv->base + UARTDM_CR); in msm_serial_fetch()
96 priv->base + UARTDM_CR); in msm_serial_fetch()
100 priv->base + UARTDM_CR); in msm_serial_fetch()
130 writel(UARTDM_CR_CMD_RESET_TX_READY, priv->base + UARTDM_CR); in msm_serial_putc()
195 writel(MSM_BOOT_UART_DM_CMD_RESET_RX, priv->base + UARTDM_CR); in uart_dm_init()
196 writel(MSM_BOOT_UART_DM_CMD_RESET_TX, priv->base + UARTDM_CR); in uart_dm_init()
/openbmc/linux/arch/arm/include/debug/
H A Dmsm.S35 @ Clear TX_READY by writing to the UARTDM_CR register