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Searched refs:TX_CLK (Results 1 – 6 of 6) sorted by relevance

/openbmc/u-boot/arch/arm/cpu/armv8/fsl-layerscape/
H A Dls1012a_serdes.c22 {0x9508, {TX_CLK, PCIE1, NONE, SATA1} },
23 {0x3905, {SGMII_FM1_DTSEC1, TX_CLK, NONE, PCIE1} },
24 {0x9305, {TX_CLK, SGMII_FM1_DTSEC2, NONE, PCIE1} },
/openbmc/u-boot/arch/arm/include/asm/arch-fsl-layerscape/
H A Dfsl_serdes.h174 TX_CLK, enumerator
/openbmc/linux/arch/powerpc/boot/dts/
H A Dmpc832x_rdb.dts180 3 23 2 0 1 0 /* TX_CLK (CLK3) */
200 3 24 2 0 1 0 /* TX_CLK (CLK10) */
/openbmc/linux/arch/arm/boot/dts/intel/socfpga/
H A Dsocfpga_arria10_socdk.dtsi75 * for TX_CLK on Arria 10.
/openbmc/u-boot/arch/arm/dts/
H A Dsocfpga_arria10_socdk.dtsi76 * for TX_CLK on Arria 10.
/openbmc/u-boot/drivers/video/
H A DKconfig333 int "SSD2828 TX_CLK frequency (in MHz)"
342 parallel LCD interface instead of TX_CLK as the PLL clock source.