Searched refs:TXIENB (Results 1 – 1 of 1) sorted by relevance
56 #define TXIENB 0x40 /* Transmit Interrupt Enable */ macro85 #define UART_ALL_IRQ_DISABLE(uart) UART_REG_CLR(uart, R_STS, RXIENB|TXIENB)87 #define UART_TX_IRQ_DISABLE(uart) UART_REG_CLR(uart, R_STS, TXIENB)89 #define UART_ALL_IRQ_ENABLE(uart) UART_REG_OR(uart, R_STS, RXIENB|TXIENB)91 #define UART_TX_IRQ_ENABLE(uart) UART_REG_OR(uart, R_STS, TXIENB)287 if ((status & TXIENB) && (status & TXEMPTY)) { in arc_serial_isr()