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Searched refs:TX0_A (Results 1 – 9 of 9) sorted by relevance

/openbmc/u-boot/board/renesas/r0p7734/
H A Dlowlevel_init.S537 # IETX_B, TX0_A, RMII0_TXD0_A,
/openbmc/linux/drivers/staging/rtl8723bs/hal/
H A DHalPhyRf_8723B.c942 u32 Oldval_0, X, TX0_A, reg; in _PHY_PathAFillIQKMatrix8723B() local
958 TX0_A = (X * Oldval_0) >> 8; in _PHY_PathAFillIQKMatrix8723B()
959 PHY_SetBBReg(pDM_Odm->Adapter, rOFDM0_XATxIQImbalance, 0x3FF, TX0_A); in _PHY_PathAFillIQKMatrix8723B()
/openbmc/u-boot/drivers/pinctrl/renesas/
H A Dpfc-r8a77995.c138 #define GPSR4_21 F_(TX0_A, IP11_27_24)
299 #define IP11_27_24 FM(TX0_A) FM(MSIOF0_SS2) FM(FSO_TOE_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)…
881 PINMUX_IPSR_MSEL(IP11_27_24, TX0_A, SEL_SCIF0_0),
H A Dpfc-r8a77990.c164 #define GPSR5_2 F_(TX0_A, IP11_15_12)
284 #define IP11_15_12 FM(TX0_A) FM(HTX1_A) FM(SSI_WS2_A) FM(RIF1_D0) F_(0, 0) F_(0, 0) F_(0, 0) F…
1066 PINMUX_IPSR_MSEL(IP11_15_12, TX0_A, SEL_SCIF0_0),
/openbmc/linux/drivers/pinctrl/renesas/
H A Dpfc-r8a77995.c147 #define GPSR4_21 F_(TX0_A, IP11_27_24)
308 #define IP11_27_24 FM(TX0_A) FM(MSIOF0_SS2) FM(FSO_TOE_N_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0)…
891 PINMUX_IPSR_MSEL(IP11_27_24, TX0_A, SEL_SCIF0_0),
H A Dpfc-r8a77990.c189 #define GPSR5_2 F_(TX0_A, IP11_15_12)
309 #define IP11_15_12 FM(TX0_A) FM(HTX1_A) FM(SSI_WS2_A) FM(RIF1_D0) F_(0, 0) F_(0, 0) F_(0, 0) F…
1096 PINMUX_IPSR_MSEL(IP11_15_12, TX0_A, SEL_SCIF0_0),
H A Dpfc-sh7734.c1313 PINMUX_IPSR_MSEL(IP11_12, TX0_A, SEL_SCIF0_0),
1623 GPIO_FN(TX0_A), GPIO_FN(HSPI_TX_A),
H A Dpfc-r8a7778.c723 PINMUX_IPSR_GPSR(IP3_9_8, TX0_A),
1451 SCIF_PFC_DAT(scif0_data_a, TX0_A, RX0_A);
H A Dpfc-r8a77470.c934 PINMUX_IPSR_MSEL(IP12_3_0, TX0_A, SEL_SCIF0_0),