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Searched refs:TSR (Results 1 – 5 of 5) sorted by relevance

/openbmc/qemu/hw/ppc/
H A Dtrace-events126 ppc4xx_fit(uint32_t ir, uint64_t tcr, uint64_t tsr) "ir %d TCR 0x%" PRIx64 " TSR 0x%" PRIx64
129 …int64_t tcr, uint64_t tsr, uint64_t reload) "ar %d ir %d TCR 0x%" PRIx64 " TSR 0x%" PRIx64 " PIT 0…
130 ppc4xx_wdt(uint64_t tcr, uint64_t tsr) "TCR 0x%" PRIx64 " TSR 0x%" PRIx64
/openbmc/u-boot/arch/sh/include/asm/
H A Dcpu_sh7722.h877 #define TSR 0xA44800B8 macro
/openbmc/u-boot/arch/powerpc/include/asm/
H A Dprocessor.h685 #define TSR SPRN_TSR /* Timer Status Register */ macro
/openbmc/u-boot/drivers/net/
H A Dmacb.c781 tsr = macb_readl(macb, TSR); in _macb_halt()
/openbmc/u-boot/arch/powerpc/cpu/mpc85xx/
H A Dstart.S293 mtspr TSR,r1 /* clear all timer exception status */