Searched refs:TRCPDCR (Results 1 – 4 of 4) sorted by relevance
| /openbmc/linux/Documentation/devicetree/bindings/arm/ |
| H A D | arm,coresight-etm.yaml | 98 TRCPDCR.PU does not have to be set on Qualcomm Technologies Inc. systems
101 watchdog counter is stopped when TRCPDCR.PU is set.
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| /openbmc/linux/drivers/hwtracing/coresight/ |
| H A D | coresight-etm4x-core.c | 501 u32 trcpdcr = etm4x_relaxed_read32(csa, TRCPDCR); in etm4_enable_hw()
507 etm4x_relaxed_write32(csa, trcpdcr | TRCPDCR_PU, TRCPDCR); in etm4_enable_hw()
880 control = etm4x_relaxed_read32(csa, TRCPDCR); in etm4_disable_hw()
882 etm4x_relaxed_write32(csa, control, TRCPDCR); in etm4_disable_hw()
1763 state->trcpdcr = etm4x_read32(csa, TRCPDCR); in __etm4_cpu_save()
1783 TRCPDCR); in __etm4_cpu_save()
1888 etm4x_relaxed_write32(csa, state->trcpdcr, TRCPDCR); in __etm4_cpu_restore()
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| H A D | coresight-etm4x.h | 84 #define TRCPDCR 0x310 macro
446 CASE_##op((val), TRCPDCR) \
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| H A D | coresight-etm4x-sysfs.c | 2549 coresight_etm4x_reg(trcpdcr, TRCPDCR),
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