Searched refs:TM_QW3_HV_PHYS (Results 1 – 5 of 5) sorted by relevance
46 case TM_QW3_HV_PHYS: in exception_mask()61 case TM_QW3_HV_PHYS: in xive_tctx_output()105 case TM_QW3_HV_PHYS: in xive_tctx_notify()163 xive_tctx_set_cppr(tctx, TM_QW3_HV_PHYS, value & 0xff); in xive_tm_set_hv_cppr()169 return xive_tctx_accept(tctx, TM_QW3_HV_PHYS); in xive_tm_ack_hv_reg()186 tctx->regs[TM_QW3_HV_PHYS + TM_WORD2] = value & 0xff; in xive_tm_vt_push()192 return tctx->regs[TM_QW3_HV_PHYS + TM_WORD2] & 0xff; in xive_tm_vt_poll()722 tctx->regs[TM_QW3_HV_PHYS + TM_PIPR] = in xive_tctx_reset()723 ipb_to_pipr(tctx->regs[TM_QW3_HV_PHYS + TM_IPB]); in xive_tctx_reset()1551 uint32_t qw3w2 = xive_tctx_word2(&tctx->regs[TM_QW3_HV_PHYS]); in xive_presenter_tctx_match()[all …]
482 uint32_t qw3w2 = xive_tctx_word2(&tctx->regs[TM_QW3_HV_PHYS]); in xive2_presenter_tctx_match()508 return TM_QW3_HV_PHYS; in xive2_presenter_tctx_match()
60 #define TM_QW3_HV_PHYS 0x030 /* Ring 0..1 */ macro
71 #define TM_QW3_HV_PHYS 0x030 /* Ring 0..1 */ macro
632 if (!xive_core_init(np, &xive_native_ops, tima, TM_QW3_HV_PHYS, in xive_native_init()