Searched refs:TM_NSR (Results 1 – 4 of 4) sorted by relevance
63 #define TM_NSR 0x0 /* + + - + */ macro
70 uint8_t nsr = regs[TM_NSR]; in xive_tctx_accept()75 if (regs[TM_NSR] & mask) { in xive_tctx_accept()94 regs[TM_NSR] &= ~mask; in xive_tctx_accept()98 regs[TM_CPPR], regs[TM_NSR]); in xive_tctx_accept()114 regs[TM_NSR] |= TM_QW1_NSR_EO; in xive_tctx_notify()117 alt_regs[TM_NSR] = (TM_QW3_NSR_HE_POOL << 6); in xive_tctx_notify()120 regs[TM_NSR] |= (TM_QW3_NSR_HE_PHYS << 6); in xive_tctx_notify()127 alt_regs[TM_CPPR], alt_regs[TM_NSR]); in xive_tctx_notify()150 cppr, regs[TM_NSR]); in xive_tctx_set_cppr()764 ring[TM_NSR], ring[TM_CPPR], ring[TM_IPB], ring[TM_LSMFB], in xive_tctx_ring_print()
415 data[0x0] = regs[TM_QW3_HV_PHYS + TM_NSR]; in xive2_tm_report_line_gen1()426 data[0x8] = regs[TM_QW1_OS + TM_NSR]; in xive2_tm_report_line_gen1()437 data[0xC] |= regs[TM_QW0_USER + TM_NSR] & 0x80; in xive2_tm_report_line_gen1()
74 #define TM_NSR 0x0 /* + + - + */ macro