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Searched refs:TM_CPPR (Results 1 – 6 of 6) sorted by relevance

/openbmc/linux/arch/powerpc/include/asm/
H A Dxive-regs.h64 #define TM_CPPR 0x1 /* - + - + */ macro
/openbmc/qemu/hw/intc/
H A Dxive.c79 regs[TM_CPPR] = cppr; in xive_tctx_accept()
90 regs[TM_CPPR], regs[TM_NSR]); in xive_tctx_accept()
93 return (nsr << 8) | regs[TM_CPPR]; in xive_tctx_accept()
100 if (regs[TM_PIPR] < regs[TM_CPPR]) { in xive_tctx_notify()
113 regs[TM_CPPR], regs[TM_NSR]); in xive_tctx_notify()
141 tctx->regs[ring + TM_CPPR] = cppr; in xive_tctx_set_cppr()
492 { XIVE_TM_OS_PAGE, TM_QW1_OS + TM_CPPR, 1, xive_tm_set_os_cppr, NULL },
494 { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_CPPR, 1, xive_tm_set_hv_cppr, NULL },
513 { XIVE_TM_OS_PAGE, TM_QW1_OS + TM_CPPR, 1, xive_tm_set_os_cppr, NULL },
515 { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_CPPR, 1, xive_tm_set_hv_cppr, NULL },
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H A Dxive2.c226 nvp.w2 = xive_set_field32(NVP2_W2_CPPR, nvp.w2, regs[TM_CPPR]); in xive2_tctx_save_os_ctx()
294 tctx->regs[TM_QW1_OS + TM_CPPR] = cppr; in xive2_tctx_restore_os_ctx()
/openbmc/linux/arch/powerpc/sysdev/xive/
H A Dcommon.c207 out_8(xive_tima + xive_tima_offset + TM_CPPR, prio); in xive_scan_interrupts()
1522 out_8(xive_tima + xive_tima_offset + TM_CPPR, 0xff); in xive_setup_cpu()
1614 out_8(xive_tima + xive_tima_offset + TM_CPPR, 0); in xive_smp_disable_cpu()
1621 out_8(xive_tima + xive_tima_offset + TM_CPPR, 0xff); in xive_smp_disable_cpu()
1644 out_8(xive_tima + xive_tima_offset + TM_CPPR, 0); in xive_teardown_cpu()
/openbmc/qemu/include/hw/ppc/
H A Dxive_regs.h75 #define TM_CPPR 0x1 /* - + - + */ macro
/openbmc/linux/arch/powerpc/kvm/
H A Dbook3s_xive.c281 __raw_writeb(xc->cppr, xive_tima + TM_QW1_OS + TM_CPPR); in xive_vm_scan_interrupts()
510 __raw_writeb(cppr, xive_tima + TM_QW1_OS + TM_CPPR); in xive_vm_h_cppr()
615 __raw_writeb(xc->cppr, xive_tima + TM_QW1_OS + TM_CPPR); in xive_vm_h_eoi()