Searched refs:TM_CPPR (Results 1 – 6 of 6) sorted by relevance
/openbmc/linux/arch/powerpc/include/asm/ |
H A D | xive-regs.h | 64 #define TM_CPPR 0x1 /* - + - + */ macro
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/openbmc/qemu/hw/intc/ |
H A D | xive.c | 79 regs[TM_CPPR] = cppr; in xive_tctx_accept() 90 regs[TM_CPPR], regs[TM_NSR]); in xive_tctx_accept() 93 return (nsr << 8) | regs[TM_CPPR]; in xive_tctx_accept() 100 if (regs[TM_PIPR] < regs[TM_CPPR]) { in xive_tctx_notify() 113 regs[TM_CPPR], regs[TM_NSR]); in xive_tctx_notify() 141 tctx->regs[ring + TM_CPPR] = cppr; in xive_tctx_set_cppr() 492 { XIVE_TM_OS_PAGE, TM_QW1_OS + TM_CPPR, 1, xive_tm_set_os_cppr, NULL }, 494 { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_CPPR, 1, xive_tm_set_hv_cppr, NULL }, 513 { XIVE_TM_OS_PAGE, TM_QW1_OS + TM_CPPR, 1, xive_tm_set_os_cppr, NULL }, 515 { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_CPPR, 1, xive_tm_set_hv_cppr, NULL }, [all …]
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H A D | xive2.c | 226 nvp.w2 = xive_set_field32(NVP2_W2_CPPR, nvp.w2, regs[TM_CPPR]); in xive2_tctx_save_os_ctx() 294 tctx->regs[TM_QW1_OS + TM_CPPR] = cppr; in xive2_tctx_restore_os_ctx()
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/openbmc/linux/arch/powerpc/sysdev/xive/ |
H A D | common.c | 207 out_8(xive_tima + xive_tima_offset + TM_CPPR, prio); in xive_scan_interrupts() 1522 out_8(xive_tima + xive_tima_offset + TM_CPPR, 0xff); in xive_setup_cpu() 1614 out_8(xive_tima + xive_tima_offset + TM_CPPR, 0); in xive_smp_disable_cpu() 1621 out_8(xive_tima + xive_tima_offset + TM_CPPR, 0xff); in xive_smp_disable_cpu() 1644 out_8(xive_tima + xive_tima_offset + TM_CPPR, 0); in xive_teardown_cpu()
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/openbmc/qemu/include/hw/ppc/ |
H A D | xive_regs.h | 75 #define TM_CPPR 0x1 /* - + - + */ macro
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/openbmc/linux/arch/powerpc/kvm/ |
H A D | book3s_xive.c | 281 __raw_writeb(xc->cppr, xive_tima + TM_QW1_OS + TM_CPPR); in xive_vm_scan_interrupts() 510 __raw_writeb(cppr, xive_tima + TM_QW1_OS + TM_CPPR); in xive_vm_h_cppr() 615 __raw_writeb(xc->cppr, xive_tima + TM_QW1_OS + TM_CPPR); in xive_vm_h_eoi()
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