Searched refs:TLB_WR (Results 1 – 7 of 7) sorted by relevance
| /openbmc/linux/arch/powerpc/include/asm/nohash/32/ |
| H A D | mmu-40x.h | 46 #define TLB_WR 0x00000100 /* Writes permitted */ macro
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| /openbmc/linux/arch/microblaze/include/asm/ |
| H A D | mmu.h | 109 # define TLB_WR 0x00000100 /* Writes permitted */ macro
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| /openbmc/qemu/target/microblaze/ |
| H A D | mmu.h | 53 #define TLB_WR 0x00000100 /* Writes permitted */ macro
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| H A D | mmu.c | 113 tlb_wr = d & TLB_WR; in mmu_translate()
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| /openbmc/linux/arch/microblaze/kernel/ |
| H A D | head.S | 229 ori r4,r4,(TLB_WR | TLB_EX) /* Set the write and execute bits */
308 ori r4,r0,(TLB_WR | TLB_EX)
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| H A D | hw_exception_handler.S | 550 andi r4, r4, PAGE_MASK | TLB_EX | TLB_WR | \
650 andi r4, r4, PAGE_MASK | TLB_EX | TLB_WR | \
721 andi r4, r4, PAGE_MASK | TLB_EX | TLB_WR | \
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| /openbmc/linux/arch/powerpc/kernel/ |
| H A D | head_40x.S | 690 ori r4,r4,(TLB_WR | TLB_EX) /* Set the write and execute bits */
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