1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Renesas RZ/G2L IRQC Driver
4 *
5 * Copyright (C) 2022 Renesas Electronics Corporation.
6 *
7 * Author: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
8 */
9
10 #include <linux/bitfield.h>
11 #include <linux/clk.h>
12 #include <linux/err.h>
13 #include <linux/io.h>
14 #include <linux/irqchip.h>
15 #include <linux/irqdomain.h>
16 #include <linux/of_address.h>
17 #include <linux/of_platform.h>
18 #include <linux/pm_runtime.h>
19 #include <linux/reset.h>
20 #include <linux/spinlock.h>
21
22 #define IRQC_IRQ_START 1
23 #define IRQC_IRQ_COUNT 8
24 #define IRQC_TINT_START (IRQC_IRQ_START + IRQC_IRQ_COUNT)
25 #define IRQC_TINT_COUNT 32
26 #define IRQC_NUM_IRQ (IRQC_TINT_START + IRQC_TINT_COUNT)
27
28 #define ISCR 0x10
29 #define IITSR 0x14
30 #define TSCR 0x20
31 #define TITSR(n) (0x24 + (n) * 4)
32 #define TITSR0_MAX_INT 16
33 #define TITSEL_WIDTH 0x2
34 #define TSSR(n) (0x30 + ((n) * 4))
35 #define TIEN BIT(7)
36 #define TSSEL_SHIFT(n) (8 * (n))
37 #define TSSEL_MASK GENMASK(7, 0)
38 #define IRQ_MASK 0x3
39
40 #define TSSR_OFFSET(n) ((n) % 4)
41 #define TSSR_INDEX(n) ((n) / 4)
42
43 #define TITSR_TITSEL_EDGE_RISING 0
44 #define TITSR_TITSEL_EDGE_FALLING 1
45 #define TITSR_TITSEL_LEVEL_HIGH 2
46 #define TITSR_TITSEL_LEVEL_LOW 3
47
48 #define IITSR_IITSEL(n, sense) ((sense) << ((n) * 2))
49 #define IITSR_IITSEL_LEVEL_LOW 0
50 #define IITSR_IITSEL_EDGE_FALLING 1
51 #define IITSR_IITSEL_EDGE_RISING 2
52 #define IITSR_IITSEL_EDGE_BOTH 3
53 #define IITSR_IITSEL_MASK(n) IITSR_IITSEL((n), 3)
54
55 #define TINT_EXTRACT_HWIRQ(x) FIELD_GET(GENMASK(15, 0), (x))
56 #define TINT_EXTRACT_GPIOINT(x) FIELD_GET(GENMASK(31, 16), (x))
57
58 struct rzg2l_irqc_priv {
59 void __iomem *base;
60 struct irq_fwspec fwspec[IRQC_NUM_IRQ];
61 raw_spinlock_t lock;
62 };
63
irq_data_to_priv(struct irq_data * data)64 static struct rzg2l_irqc_priv *irq_data_to_priv(struct irq_data *data)
65 {
66 return data->domain->host_data;
67 }
68
rzg2l_clear_irq_int(struct rzg2l_irqc_priv * priv,unsigned int hwirq)69 static void rzg2l_clear_irq_int(struct rzg2l_irqc_priv *priv, unsigned int hwirq)
70 {
71 unsigned int hw_irq = hwirq - IRQC_IRQ_START;
72 u32 bit = BIT(hw_irq);
73 u32 iitsr, iscr;
74
75 iscr = readl_relaxed(priv->base + ISCR);
76 iitsr = readl_relaxed(priv->base + IITSR);
77
78 /*
79 * ISCR can only be cleared if the type is falling-edge, rising-edge or
80 * falling/rising-edge.
81 */
82 if ((iscr & bit) && (iitsr & IITSR_IITSEL_MASK(hw_irq))) {
83 writel_relaxed(iscr & ~bit, priv->base + ISCR);
84 /*
85 * Enforce that the posted write is flushed to prevent that the
86 * just handled interrupt is raised again.
87 */
88 readl_relaxed(priv->base + ISCR);
89 }
90 }
91
rzg2l_clear_tint_int(struct rzg2l_irqc_priv * priv,unsigned int hwirq)92 static void rzg2l_clear_tint_int(struct rzg2l_irqc_priv *priv, unsigned int hwirq)
93 {
94 u32 bit = BIT(hwirq - IRQC_TINT_START);
95 u32 reg;
96
97 reg = readl_relaxed(priv->base + TSCR);
98 if (reg & bit) {
99 writel_relaxed(reg & ~bit, priv->base + TSCR);
100 /*
101 * Enforce that the posted write is flushed to prevent that the
102 * just handled interrupt is raised again.
103 */
104 readl_relaxed(priv->base + TSCR);
105 }
106 }
107
rzg2l_irqc_eoi(struct irq_data * d)108 static void rzg2l_irqc_eoi(struct irq_data *d)
109 {
110 struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
111 unsigned int hw_irq = irqd_to_hwirq(d);
112
113 raw_spin_lock(&priv->lock);
114 if (hw_irq >= IRQC_IRQ_START && hw_irq <= IRQC_IRQ_COUNT)
115 rzg2l_clear_irq_int(priv, hw_irq);
116 else if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ)
117 rzg2l_clear_tint_int(priv, hw_irq);
118 raw_spin_unlock(&priv->lock);
119 irq_chip_eoi_parent(d);
120 }
121
rzg2l_irqc_irq_disable(struct irq_data * d)122 static void rzg2l_irqc_irq_disable(struct irq_data *d)
123 {
124 unsigned int hw_irq = irqd_to_hwirq(d);
125
126 if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) {
127 struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
128 u32 offset = hw_irq - IRQC_TINT_START;
129 u32 tssr_offset = TSSR_OFFSET(offset);
130 u8 tssr_index = TSSR_INDEX(offset);
131 u32 reg;
132
133 raw_spin_lock(&priv->lock);
134 reg = readl_relaxed(priv->base + TSSR(tssr_index));
135 reg &= ~(TIEN << TSSEL_SHIFT(tssr_offset));
136 writel_relaxed(reg, priv->base + TSSR(tssr_index));
137 raw_spin_unlock(&priv->lock);
138 }
139 irq_chip_disable_parent(d);
140 }
141
rzg2l_irqc_irq_enable(struct irq_data * d)142 static void rzg2l_irqc_irq_enable(struct irq_data *d)
143 {
144 unsigned int hw_irq = irqd_to_hwirq(d);
145
146 if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ) {
147 struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
148 u32 offset = hw_irq - IRQC_TINT_START;
149 u32 tssr_offset = TSSR_OFFSET(offset);
150 u8 tssr_index = TSSR_INDEX(offset);
151 u32 reg;
152
153 raw_spin_lock(&priv->lock);
154 reg = readl_relaxed(priv->base + TSSR(tssr_index));
155 reg |= TIEN << TSSEL_SHIFT(tssr_offset);
156 writel_relaxed(reg, priv->base + TSSR(tssr_index));
157 raw_spin_unlock(&priv->lock);
158 }
159 irq_chip_enable_parent(d);
160 }
161
rzg2l_irq_set_type(struct irq_data * d,unsigned int type)162 static int rzg2l_irq_set_type(struct irq_data *d, unsigned int type)
163 {
164 struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
165 unsigned int hwirq = irqd_to_hwirq(d);
166 u32 iitseln = hwirq - IRQC_IRQ_START;
167 bool clear_irq_int = false;
168 u16 sense, tmp;
169
170 switch (type & IRQ_TYPE_SENSE_MASK) {
171 case IRQ_TYPE_LEVEL_LOW:
172 sense = IITSR_IITSEL_LEVEL_LOW;
173 break;
174
175 case IRQ_TYPE_EDGE_FALLING:
176 sense = IITSR_IITSEL_EDGE_FALLING;
177 clear_irq_int = true;
178 break;
179
180 case IRQ_TYPE_EDGE_RISING:
181 sense = IITSR_IITSEL_EDGE_RISING;
182 clear_irq_int = true;
183 break;
184
185 case IRQ_TYPE_EDGE_BOTH:
186 sense = IITSR_IITSEL_EDGE_BOTH;
187 clear_irq_int = true;
188 break;
189
190 default:
191 return -EINVAL;
192 }
193
194 raw_spin_lock(&priv->lock);
195 tmp = readl_relaxed(priv->base + IITSR);
196 tmp &= ~IITSR_IITSEL_MASK(iitseln);
197 tmp |= IITSR_IITSEL(iitseln, sense);
198 if (clear_irq_int)
199 rzg2l_clear_irq_int(priv, hwirq);
200 writel_relaxed(tmp, priv->base + IITSR);
201 raw_spin_unlock(&priv->lock);
202
203 return 0;
204 }
205
rzg2l_disable_tint_and_set_tint_source(struct irq_data * d,struct rzg2l_irqc_priv * priv,u32 reg,u32 tssr_offset,u8 tssr_index)206 static u32 rzg2l_disable_tint_and_set_tint_source(struct irq_data *d, struct rzg2l_irqc_priv *priv,
207 u32 reg, u32 tssr_offset, u8 tssr_index)
208 {
209 u32 tint = (u32)(uintptr_t)irq_data_get_irq_chip_data(d);
210 u32 tien = reg & (TIEN << TSSEL_SHIFT(tssr_offset));
211
212 /* Clear the relevant byte in reg */
213 reg &= ~(TSSEL_MASK << TSSEL_SHIFT(tssr_offset));
214 /* Set TINT and leave TIEN clear */
215 reg |= tint << TSSEL_SHIFT(tssr_offset);
216 writel_relaxed(reg, priv->base + TSSR(tssr_index));
217
218 return reg | tien;
219 }
220
rzg2l_tint_set_edge(struct irq_data * d,unsigned int type)221 static int rzg2l_tint_set_edge(struct irq_data *d, unsigned int type)
222 {
223 struct rzg2l_irqc_priv *priv = irq_data_to_priv(d);
224 unsigned int hwirq = irqd_to_hwirq(d);
225 u32 titseln = hwirq - IRQC_TINT_START;
226 u32 tssr_offset = TSSR_OFFSET(titseln);
227 u8 tssr_index = TSSR_INDEX(titseln);
228 u8 index, sense;
229 u32 reg, tssr;
230
231 switch (type & IRQ_TYPE_SENSE_MASK) {
232 case IRQ_TYPE_EDGE_RISING:
233 sense = TITSR_TITSEL_EDGE_RISING;
234 break;
235
236 case IRQ_TYPE_EDGE_FALLING:
237 sense = TITSR_TITSEL_EDGE_FALLING;
238 break;
239
240 default:
241 return -EINVAL;
242 }
243
244 index = 0;
245 if (titseln >= TITSR0_MAX_INT) {
246 titseln -= TITSR0_MAX_INT;
247 index = 1;
248 }
249
250 raw_spin_lock(&priv->lock);
251 tssr = readl_relaxed(priv->base + TSSR(tssr_index));
252 tssr = rzg2l_disable_tint_and_set_tint_source(d, priv, tssr, tssr_offset, tssr_index);
253 reg = readl_relaxed(priv->base + TITSR(index));
254 reg &= ~(IRQ_MASK << (titseln * TITSEL_WIDTH));
255 reg |= sense << (titseln * TITSEL_WIDTH);
256 writel_relaxed(reg, priv->base + TITSR(index));
257 rzg2l_clear_tint_int(priv, hwirq);
258 writel_relaxed(tssr, priv->base + TSSR(tssr_index));
259 raw_spin_unlock(&priv->lock);
260
261 return 0;
262 }
263
rzg2l_irqc_set_type(struct irq_data * d,unsigned int type)264 static int rzg2l_irqc_set_type(struct irq_data *d, unsigned int type)
265 {
266 unsigned int hw_irq = irqd_to_hwirq(d);
267 int ret = -EINVAL;
268
269 if (hw_irq >= IRQC_IRQ_START && hw_irq <= IRQC_IRQ_COUNT)
270 ret = rzg2l_irq_set_type(d, type);
271 else if (hw_irq >= IRQC_TINT_START && hw_irq < IRQC_NUM_IRQ)
272 ret = rzg2l_tint_set_edge(d, type);
273 if (ret)
274 return ret;
275
276 return irq_chip_set_type_parent(d, IRQ_TYPE_LEVEL_HIGH);
277 }
278
279 static const struct irq_chip irqc_chip = {
280 .name = "rzg2l-irqc",
281 .irq_eoi = rzg2l_irqc_eoi,
282 .irq_mask = irq_chip_mask_parent,
283 .irq_unmask = irq_chip_unmask_parent,
284 .irq_disable = rzg2l_irqc_irq_disable,
285 .irq_enable = rzg2l_irqc_irq_enable,
286 .irq_get_irqchip_state = irq_chip_get_parent_state,
287 .irq_set_irqchip_state = irq_chip_set_parent_state,
288 .irq_retrigger = irq_chip_retrigger_hierarchy,
289 .irq_set_type = rzg2l_irqc_set_type,
290 .flags = IRQCHIP_MASK_ON_SUSPEND |
291 IRQCHIP_SET_TYPE_MASKED |
292 IRQCHIP_SKIP_SET_WAKE,
293 };
294
rzg2l_irqc_alloc(struct irq_domain * domain,unsigned int virq,unsigned int nr_irqs,void * arg)295 static int rzg2l_irqc_alloc(struct irq_domain *domain, unsigned int virq,
296 unsigned int nr_irqs, void *arg)
297 {
298 struct rzg2l_irqc_priv *priv = domain->host_data;
299 unsigned long tint = 0;
300 irq_hw_number_t hwirq;
301 unsigned int type;
302 int ret;
303
304 ret = irq_domain_translate_twocell(domain, arg, &hwirq, &type);
305 if (ret)
306 return ret;
307
308 /*
309 * For TINT interrupts ie where pinctrl driver is child of irqc domain
310 * the hwirq and TINT are encoded in fwspec->param[0].
311 * hwirq for TINT range from 9-40, hwirq is embedded 0-15 bits and TINT
312 * from 16-31 bits. TINT from the pinctrl driver needs to be programmed
313 * in IRQC registers to enable a given gpio pin as interrupt.
314 */
315 if (hwirq > IRQC_IRQ_COUNT) {
316 tint = TINT_EXTRACT_GPIOINT(hwirq);
317 hwirq = TINT_EXTRACT_HWIRQ(hwirq);
318
319 if (hwirq < IRQC_TINT_START)
320 return -EINVAL;
321 }
322
323 if (hwirq > (IRQC_NUM_IRQ - 1))
324 return -EINVAL;
325
326 ret = irq_domain_set_hwirq_and_chip(domain, virq, hwirq, &irqc_chip,
327 (void *)(uintptr_t)tint);
328 if (ret)
329 return ret;
330
331 return irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, &priv->fwspec[hwirq]);
332 }
333
334 static const struct irq_domain_ops rzg2l_irqc_domain_ops = {
335 .alloc = rzg2l_irqc_alloc,
336 .free = irq_domain_free_irqs_common,
337 .translate = irq_domain_translate_twocell,
338 };
339
rzg2l_irqc_parse_interrupts(struct rzg2l_irqc_priv * priv,struct device_node * np)340 static int rzg2l_irqc_parse_interrupts(struct rzg2l_irqc_priv *priv,
341 struct device_node *np)
342 {
343 struct of_phandle_args map;
344 unsigned int i;
345 int ret;
346
347 for (i = 0; i < IRQC_NUM_IRQ; i++) {
348 ret = of_irq_parse_one(np, i, &map);
349 if (ret)
350 return ret;
351 of_phandle_args_to_fwspec(np, map.args, map.args_count,
352 &priv->fwspec[i]);
353 }
354
355 return 0;
356 }
357
rzg2l_irqc_init(struct device_node * node,struct device_node * parent)358 static int rzg2l_irqc_init(struct device_node *node, struct device_node *parent)
359 {
360 struct irq_domain *irq_domain, *parent_domain;
361 struct platform_device *pdev;
362 struct reset_control *resetn;
363 struct rzg2l_irqc_priv *priv;
364 int ret;
365
366 pdev = of_find_device_by_node(node);
367 if (!pdev)
368 return -ENODEV;
369
370 parent_domain = irq_find_host(parent);
371 if (!parent_domain) {
372 dev_err(&pdev->dev, "cannot find parent domain\n");
373 return -ENODEV;
374 }
375
376 priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
377 if (!priv)
378 return -ENOMEM;
379
380 priv->base = devm_of_iomap(&pdev->dev, pdev->dev.of_node, 0, NULL);
381 if (IS_ERR(priv->base))
382 return PTR_ERR(priv->base);
383
384 ret = rzg2l_irqc_parse_interrupts(priv, node);
385 if (ret) {
386 dev_err(&pdev->dev, "cannot parse interrupts: %d\n", ret);
387 return ret;
388 }
389
390 resetn = devm_reset_control_get_exclusive(&pdev->dev, NULL);
391 if (IS_ERR(resetn))
392 return PTR_ERR(resetn);
393
394 ret = reset_control_deassert(resetn);
395 if (ret) {
396 dev_err(&pdev->dev, "failed to deassert resetn pin, %d\n", ret);
397 return ret;
398 }
399
400 pm_runtime_enable(&pdev->dev);
401 ret = pm_runtime_resume_and_get(&pdev->dev);
402 if (ret < 0) {
403 dev_err(&pdev->dev, "pm_runtime_resume_and_get failed: %d\n", ret);
404 goto pm_disable;
405 }
406
407 raw_spin_lock_init(&priv->lock);
408
409 irq_domain = irq_domain_add_hierarchy(parent_domain, 0, IRQC_NUM_IRQ,
410 node, &rzg2l_irqc_domain_ops,
411 priv);
412 if (!irq_domain) {
413 dev_err(&pdev->dev, "failed to add irq domain\n");
414 ret = -ENOMEM;
415 goto pm_put;
416 }
417
418 return 0;
419
420 pm_put:
421 pm_runtime_put(&pdev->dev);
422 pm_disable:
423 pm_runtime_disable(&pdev->dev);
424 reset_control_assert(resetn);
425 return ret;
426 }
427
428 IRQCHIP_PLATFORM_DRIVER_BEGIN(rzg2l_irqc)
429 IRQCHIP_MATCH("renesas,rzg2l-irqc", rzg2l_irqc_init)
430 IRQCHIP_PLATFORM_DRIVER_END(rzg2l_irqc)
431 MODULE_AUTHOR("Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>");
432 MODULE_DESCRIPTION("Renesas RZ/G2L IRQC Driver");
433