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Searched refs:TIMING_CFG1_CASLAT_50 (Results 1 – 2 of 2) sorted by relevance

/openbmc/u-boot/include/configs/
H A Dkm8360.h121 #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \
/openbmc/u-boot/include/
H A Dmpc83xx.h1200 #define TIMING_CFG1_CASLAT_50 0x00090000 /* CAS latency = 5.0 */ macro