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Searched refs:TIMING_CFG1_CASLAT_40 (Results 1 – 3 of 3) sorted by relevance

/openbmc/u-boot/include/configs/km/
H A Dkm8321-common.h98 #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \
H A Dkm8309-common.h134 #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_40) | \
/openbmc/u-boot/include/
H A Dmpc83xx.h1198 #define TIMING_CFG1_CASLAT_40 0x00070000 /* CAS latency = 4.0 */ macro