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Searched refs:TIME_STAMP_INT_ENABLE (Results 1 – 15 of 15) sorted by relevance

/openbmc/linux/drivers/gpu/drm/radeon/
H A Dcik.c7051 cp_m1p0 = RREG32(CP_ME1_PIPE0_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set()
7052 cp_m1p1 = RREG32(CP_ME1_PIPE1_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set()
7053 cp_m1p2 = RREG32(CP_ME1_PIPE2_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set()
7054 cp_m1p3 = RREG32(CP_ME1_PIPE3_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set()
7055 cp_m2p0 = RREG32(CP_ME2_PIPE0_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set()
7056 cp_m2p1 = RREG32(CP_ME2_PIPE1_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set()
7057 cp_m2p2 = RREG32(CP_ME2_PIPE2_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set()
7058 cp_m2p3 = RREG32(CP_ME2_PIPE3_INT_CNTL) & ~TIME_STAMP_INT_ENABLE; in cik_irq_set()
7063 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in cik_irq_set()
7071 cp_m1p0 |= TIME_STAMP_INT_ENABLE; in cik_irq_set()
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H A Dcikd.h1337 # define TIME_STAMP_INT_ENABLE (1 << 26) macro
1369 # define TIME_STAMP_INT_ENABLE (1 << 26) macro
H A Dnid.h497 # define TIME_STAMP_INT_ENABLE (1 << 26) macro
H A Devergreen.c4527 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in evergreen_irq_set()
4531 cp_int_cntl1 |= TIME_STAMP_INT_ENABLE; in evergreen_irq_set()
4535 cp_int_cntl2 |= TIME_STAMP_INT_ENABLE; in evergreen_irq_set()
4541 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in evergreen_irq_set()
H A Dsid.h1282 # define TIME_STAMP_INT_ENABLE (1 << 26) macro
H A Dsi.c6082 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in si_irq_set()
6086 cp_int_cntl1 |= TIME_STAMP_INT_ENABLE; in si_irq_set()
6090 cp_int_cntl2 |= TIME_STAMP_INT_ENABLE; in si_irq_set()
H A Devergreend.h1250 # define TIME_STAMP_INT_ENABLE (1 << 26) macro
H A Dr600d.h718 # define TIME_STAMP_INT_ENABLE (1 << 26) macro
H A Dr600.c3822 cp_int_cntl |= TIME_STAMP_INT_ENABLE; in r600_irq_set()
/openbmc/linux/drivers/gpu/drm/amd/amdgpu/
H A Dsid.h1310 # define TIME_STAMP_INT_ENABLE (1 << 26) macro
H A Dgfx_v11_0.c5737 TIME_STAMP_INT_ENABLE, 0); in gfx_v11_0_set_gfx_eop_interrupt_state()
5745 TIME_STAMP_INT_ENABLE, 1); in gfx_v11_0_set_gfx_eop_interrupt_state()
5794 TIME_STAMP_INT_ENABLE, 0); in gfx_v11_0_set_compute_eop_interrupt_state()
5802 TIME_STAMP_INT_ENABLE, 1); in gfx_v11_0_set_compute_eop_interrupt_state()
H A Dgfx_v9_4_3.c2743 TIME_STAMP_INT_ENABLE, 0); in gfx_v9_4_3_xcc_set_compute_eop_interrupt_state()
2749 TIME_STAMP_INT_ENABLE, 1); in gfx_v9_4_3_xcc_set_compute_eop_interrupt_state()
H A Dgfx_v9_0.c5724 TIME_STAMP_INT_ENABLE, in gfx_v9_0_set_gfx_eop_interrupt_state()
5771 TIME_STAMP_INT_ENABLE, 0); in gfx_v9_0_set_compute_eop_interrupt_state()
5777 TIME_STAMP_INT_ENABLE, 1); in gfx_v9_0_set_compute_eop_interrupt_state()
H A Dgfx_v10_0.c8784 TIME_STAMP_INT_ENABLE, 0); in gfx_v10_0_set_gfx_eop_interrupt_state()
8790 TIME_STAMP_INT_ENABLE, 1); in gfx_v10_0_set_gfx_eop_interrupt_state()
8837 TIME_STAMP_INT_ENABLE, 0); in gfx_v10_0_set_compute_eop_interrupt_state()
8843 TIME_STAMP_INT_ENABLE, 1); in gfx_v10_0_set_compute_eop_interrupt_state()
H A Dgfx_v8_0.c6413 WREG32_FIELD(CP_INT_CNTL_RING0, TIME_STAMP_INT_ENABLE, in gfx_v8_0_set_gfx_eop_interrupt_state()