Searched refs:TILE_SPLIT (Results 1 – 16 of 16) sorted by relevance
436 TILE_SPLIT(split_equal_to_row_size); in gfx_v6_0_tiling_mode_table_init()526 TILE_SPLIT(split_equal_to_row_size); in gfx_v6_0_tiling_mode_table_init()537 TILE_SPLIT(split_equal_to_row_size); in gfx_v6_0_tiling_mode_table_init()545 TILE_SPLIT(split_equal_to_row_size); in gfx_v6_0_tiling_mode_table_init()783 TILE_SPLIT(split_equal_to_row_size); in gfx_v6_0_tiling_mode_table_init()791 TILE_SPLIT(split_equal_to_row_size); in gfx_v6_0_tiling_mode_table_init()866 TILE_SPLIT(split_equal_to_row_size); in gfx_v6_0_tiling_mode_table_init()956 TILE_SPLIT(split_equal_to_row_size); in gfx_v6_0_tiling_mode_table_init()967 TILE_SPLIT(split_equal_to_row_size); in gfx_v6_0_tiling_mode_table_init()975 TILE_SPLIT(split_equal_to_row_size); in gfx_v6_0_tiling_mode_table_init()[all …]
2094 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | in gfx_v8_0_tiling_mode_table_init()2110 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | in gfx_v8_0_tiling_mode_table_init()2114 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | in gfx_v8_0_tiling_mode_table_init()2118 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | in gfx_v8_0_tiling_mode_table_init()2266 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | in gfx_v8_0_tiling_mode_table_init()2282 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | in gfx_v8_0_tiling_mode_table_init()2286 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | in gfx_v8_0_tiling_mode_table_init()2290 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | in gfx_v8_0_tiling_mode_table_init()2294 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_2KB) | in gfx_v8_0_tiling_mode_table_init()2455 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | in gfx_v8_0_tiling_mode_table_init()[all …]
1021 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | in gfx_v7_0_tiling_mode_table_init()1038 TILE_SPLIT(split_equal_to_row_size)); in gfx_v7_0_tiling_mode_table_init()1045 TILE_SPLIT(split_equal_to_row_size)); in gfx_v7_0_tiling_mode_table_init()1188 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | in gfx_v7_0_tiling_mode_table_init()1205 TILE_SPLIT(split_equal_to_row_size)); in gfx_v7_0_tiling_mode_table_init()1209 TILE_SPLIT(split_equal_to_row_size)); in gfx_v7_0_tiling_mode_table_init()1213 TILE_SPLIT(split_equal_to_row_size)); in gfx_v7_0_tiling_mode_table_init()1217 TILE_SPLIT(split_equal_to_row_size)); in gfx_v7_0_tiling_mode_table_init()1374 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | in gfx_v7_0_tiling_mode_table_init()1391 TILE_SPLIT(split_equal_to_row_size)); in gfx_v7_0_tiling_mode_table_init()[all …]
191 # define TILE_SPLIT(x) ((x) << 11) macro
1134 AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT) > 6) in amdgpu_bo_set_tiling_flags()
1195 # define TILE_SPLIT(x) ((x) << 11) macro
1913 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in dce_v8_0_crtc_do_set_base()
1944 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in dce_v6_0_crtc_do_set_base()
1988 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in dce_v10_0_crtc_do_set_base()
2038 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in dce_v11_0_crtc_do_set_base()
2518 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | in si_tiling_mode_table_init()2554 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | in si_tiling_mode_table_init()2563 TILE_SPLIT(split_equal_to_row_size) | in si_tiling_mode_table_init()2572 TILE_SPLIT(split_equal_to_row_size) | in si_tiling_mode_table_init()2581 TILE_SPLIT(split_equal_to_row_size) | in si_tiling_mode_table_init()2590 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B) | in si_tiling_mode_table_init()2671 TILE_SPLIT(split_equal_to_row_size) | in si_tiling_mode_table_init()2778 TILE_SPLIT(split_equal_to_row_size) | in si_tiling_mode_table_init()2787 TILE_SPLIT(split_equal_to_row_size) | in si_tiling_mode_table_init()2796 TILE_SPLIT(split_equal_to_row_size) | in si_tiling_mode_table_init()[all …]
2360 TILE_SPLIT(ADDR_SURF_TILE_SPLIT_64B)); in cik_tiling_mode_table_init()2376 TILE_SPLIT(split_equal_to_row_size)); in cik_tiling_mode_table_init()2387 TILE_SPLIT(split_equal_to_row_size)); in cik_tiling_mode_table_init()2519 TILE_SPLIT(split_equal_to_row_size)); in cik_tiling_mode_table_init()2530 TILE_SPLIT(split_equal_to_row_size)); in cik_tiling_mode_table_init()2663 TILE_SPLIT(split_equal_to_row_size)); in cik_tiling_mode_table_init()2674 TILE_SPLIT(split_equal_to_row_size)); in cik_tiling_mode_table_init()2743 TILE_SPLIT(split_equal_to_row_size)); in cik_tiling_mode_table_init()2754 TILE_SPLIT(split_equal_to_row_size)); in cik_tiling_mode_table_init()2887 TILE_SPLIT(split_equal_to_row_size)); in cik_tiling_mode_table_init()[all …]
1198 # define TILE_SPLIT(x) ((x) << 11) macro
1240 # define TILE_SPLIT(x) ((x) << 11) macro
191 tile_split = AMDGPU_TILING_GET(tiling_flags, TILE_SPLIT); in fill_gfx8_tiling_info_from_flags()
1730 typedef enum TILE_SPLIT { enum1738 } TILE_SPLIT; typedef