Searched refs:TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_RSVD1_MASK (Results 1 – 1 of 1) sorted by relevance
1824 #define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_RSVD1_MASK 0xF8000000u macro1826 …t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_RSVD1_MASK)