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Searched refs:TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_RSVD1_MASK (Results 1 – 1 of 1) sorted by relevance

/openbmc/u-boot/arch/arm/include/asm/arch-mx7/
H A Dcrm_regs.h1824 #define TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_RSVD1_MASK 0xF8000000u macro
1826 …t)(x))<<TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_RSVD1_SHIFT))&TEMPMON_HW_ANADIG_TEMPSENSE0_CLR_RSVD1_MASK)