Searched refs:TEGRA_IVC_ALIGN (Results 1 – 2 of 2) sorted by relevance
10 #define TEGRA_IVC_ALIGN 64 macro62 uint8_t w_align[TEGRA_IVC_ALIGN];67 uint8_t r_align[TEGRA_IVC_ALIGN];76 invalidate_dcache_range(base, base + TEGRA_IVC_ALIGN); in tegra_ivc_invalidate_counter()84 flush_dcache_range(base, base + TEGRA_IVC_ALIGN); in tegra_ivc_flush_counter()488 (TEGRA_IVC_ALIGN - 1)); in check_ivc_params()490 (TEGRA_IVC_ALIGN - 1)); in check_ivc_params()492 (TEGRA_IVC_ALIGN - 1)); in check_ivc_params()503 if ((qbase1 & (TEGRA_IVC_ALIGN - 1)) || in check_ivc_params()504 (qbase2 & (TEGRA_IVC_ALIGN - 1))) { in check_ivc_params()[all …]
8 #define TEGRA_IVC_ALIGN 64 macro61 u8 pad[TEGRA_IVC_ALIGN];67 u8 pad[TEGRA_IVC_ALIGN];558 return ALIGN(size, TEGRA_IVC_ALIGN); in tegra_ivc_align()564 if (!IS_ALIGNED(queue_size, TEGRA_IVC_ALIGN)) { in tegra_ivc_total_queue_size()566 __func__, queue_size, TEGRA_IVC_ALIGN); in tegra_ivc_total_queue_size()578 TEGRA_IVC_ALIGN)); in tegra_ivc_check_params()580 TEGRA_IVC_ALIGN)); in tegra_ivc_check_params()582 TEGRA_IVC_ALIGN)); in tegra_ivc_check_params()598 if (!IS_ALIGNED(rx, TEGRA_IVC_ALIGN)) { in tegra_ivc_check_params()[all …]