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Searched refs:TEGRA30_CLK_PLL_C (Results 1 – 8 of 8) sorted by relevance

/openbmc/linux/drivers/clk/tegra/
H A Dclk-tegra30.c538 { .con_id = "pll_c", .dt_id = TEGRA30_CLK_PLL_C },
1222 { TEGRA30_CLK_PLL_C, TEGRA30_CLK_CLK_MAX, 600000000, 0 },
1223 { TEGRA30_CLK_HOST1X, TEGRA30_CLK_PLL_C, 150000000, 0 },
1225 { TEGRA30_CLK_GR2D, TEGRA30_CLK_PLL_C, 300000000, 0 },
1226 { TEGRA30_CLK_GR3D, TEGRA30_CLK_PLL_C, 300000000, 0 },
1227 { TEGRA30_CLK_GR3D2, TEGRA30_CLK_PLL_C, 300000000, 0 },
1229 { TEGRA30_CLK_VDE, TEGRA30_CLK_PLL_C, 300000000, 0 },
1371 clks[TEGRA30_CLK_PLL_C] = clk; in tegra30_car_probe()
/openbmc/linux/include/dt-bindings/clock/
H A Dtegra30-car.h202 #define TEGRA30_CLK_PLL_C 175 macro
/openbmc/u-boot/include/dt-bindings/clock/
H A Dtegra30-car.h199 #define TEGRA30_CLK_PLL_C 175 macro
/openbmc/linux/arch/arm/boot/dts/nvidia/
H A Dtegra30-asus-nexus7-grouper-common.dtsi997 assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_C>;
H A Dtegra30.dtsi402 clocks = <&tegra_car TEGRA30_CLK_PLL_C>;
H A Dtegra30-asus-transformer-common.dtsi1413 assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_C>;
H A Dtegra30-pegatron-chagall.dts2526 assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_C>;
H A Dtegra30-ouya.dts4506 assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_C>;