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Searched refs:TEGRA30_CLK_PLL_A_OUT0 (Results 1 – 14 of 14) sorted by relevance

/openbmc/linux/drivers/clk/tegra/
H A Dclk-tegra30.c555 { .con_id = "pll_a_out0", .dt_id = TEGRA30_CLK_PLL_A_OUT0 },
806 [tegra_clk_pll_a_out0] = { .dt_id = TEGRA30_CLK_PLL_A_OUT0, .present = true },
1205 { TEGRA30_CLK_PLL_A_OUT0, TEGRA30_CLK_CLK_MAX, 11289600, 0 },
1206 { TEGRA30_CLK_I2S0, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },
1207 { TEGRA30_CLK_I2S1, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },
1208 { TEGRA30_CLK_I2S2, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },
1209 { TEGRA30_CLK_I2S3, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },
1210 { TEGRA30_CLK_I2S4, TEGRA30_CLK_PLL_A_OUT0, 11289600, 0 },
/openbmc/linux/include/dt-bindings/clock/
H A Dtegra30-car.h212 #define TEGRA30_CLK_PLL_A_OUT0 185 macro
/openbmc/u-boot/include/dt-bindings/clock/
H A Dtegra30-car.h209 #define TEGRA30_CLK_PLL_A_OUT0 185 macro
/openbmc/linux/Documentation/devicetree/bindings/sound/
H A Dnvidia,tegra-audio-sgtl5000.yaml64 <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
H A Dnvidia,tegra-audio-rt5631.yaml82 <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
H A Dnvidia,tegra-audio-max9808x.yaml87 <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
/openbmc/linux/arch/arm/boot/dts/nvidia/
H A Dtegra30-cardhu.dtsi669 <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
676 assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
H A Dtegra30-colibri.dtsi1055 <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
1062 assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
H A Dtegra30-apalis.dtsi1177 <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
1184 assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
H A Dtegra30-apalis-v1.1.dtsi1194 <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
1201 assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
H A Dtegra30-asus-nexus7-grouper-common.dtsi1223 <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
1230 assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
H A Dtegra30-asus-transformer-common.dtsi1683 <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
1690 assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
H A Dtegra30-beaver.dts2130 <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
2137 assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
H A Dtegra30-pegatron-chagall.dts2764 <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
2771 assigned-clock-parents = <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,