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Searched refs:TEGRA20_CLK_PLL_P_OUT3 (Results 1 – 7 of 7) sorted by relevance

/openbmc/linux/include/dt-bindings/clock/
H A Dtegra20-car.h147 #define TEGRA20_CLK_PLL_P_OUT3 124 macro
/openbmc/u-boot/include/dt-bindings/clock/
H A Dtegra20-car.h146 #define TEGRA20_CLK_PLL_P_OUT3 124 macro
/openbmc/linux/Documentation/devicetree/bindings/soc/tegra/
H A Dnvidia,nvec.yaml80 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
/openbmc/u-boot/arch/arm/dts/
H A Dtegra20.dtsi410 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
440 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
456 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
472 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
H A Dtegra20-paz00.dts328 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
/openbmc/linux/arch/arm/boot/dts/nvidia/
H A Dtegra20.dtsi547 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
577 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
593 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
609 <&tegra_car TEGRA20_CLK_PLL_P_OUT3>;
/openbmc/linux/drivers/clk/tegra/
H A Dclk-tegra20.c425 { .con_id = "pll_p_out3", .dt_id = TEGRA20_CLK_PLL_P_OUT3 },
547 [tegra_clk_pll_p_out3] = { .dt_id = TEGRA20_CLK_PLL_P_OUT3, .present = true },
1016 { TEGRA20_CLK_PLL_P_OUT3, TEGRA20_CLK_CLK_MAX, 72000000, 1 },