Searched refs:TEGRA186_CLK_PLL_A_OUT0 (Results 1 – 4 of 4) sorted by relevance
153 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;167 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;181 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;195 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;209 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;223 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;331 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;343 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;2058 <&bpmp TEGRA186_CLK_PLL_A_OUT0>;2061 <&bpmp TEGRA186_CLK_PLL_A_OUT0>,[all …]
95 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLL_A_OUT0>;
712 #define TEGRA186_CLK_PLL_A_OUT0 246 macro
711 #define TEGRA186_CLK_PLL_A_OUT0 246 macro