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Searched refs:TEGRA186_CLK_PLLP_OUT0 (Results 1 – 3 of 3) sorted by relevance

/openbmc/linux/include/dt-bindings/clock/
H A Dtegra186-clock.h748 #define TEGRA186_CLK_PLLP_OUT0 269 macro
/openbmc/u-boot/include/dt-bindings/clock/
H A Dtegra186-clock.h747 #define TEGRA186_CLK_PLLP_OUT0 269 macro
/openbmc/linux/arch/arm64/boot/dts/nvidia/
H A Dtegra186.dtsi138 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>;
873 <&bpmp TEGRA186_CLK_PLLP_OUT0>;
874 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>;
978 assigned-clock-parents = <&bpmp TEGRA186_CLK_PLLP_OUT0>,